Searched refs:cr (Results 1 - 25 of 130) sorted by relevance

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/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610.c121 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
122 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
123 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
125 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
127 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
131 &ddrmr->cr[13]);
134 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
136 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
138 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
140 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[1
[all...]
H A Dddrmc-vf610-calibration.c111 while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
114 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
118 do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
122 do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
145 (readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF;
146 u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF;
159 writel(0x40703030, &ddrmr->cr[144]);
160 writel(0x40, &ddrmr->cr[145]);
161 writel(0x40, &ddrmr->cr[146]);
163 tmp = readl(&ddrmr->cr[14
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/u-boot/arch/arm/mach-at91/
H A Dmpddrc.c27 static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) argument
33 (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
46 u32 ba_off, cr; local
49 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
50 if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
51 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
59 writel(mpddr_value->cr, &mpddr->cr);
94 cr = readl(&mpddr->cr);
[all...]
/u-boot/drivers/timer/
H A Dfttmr010_timer.c41 unsigned int cr; local
51 writel(0, &tmr->cr);
65 cr = readl(&tmr->cr);
66 cr |= FTTMR010_TM3_CLOCK; /* use external clock */
67 cr |= FTTMR010_TM3_ENABLE;
68 writel(cr, &tmr->cr);
H A Dimx-gpt-timer.c37 u32 cr; member in struct:imx_gpt_timer_regs
66 setbits_le32(&regs->cr, GPT_CR_SWR);
69 while (readl(&regs->cr) & GPT_CR_SWR)
82 writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, &regs->cr);
92 writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, &regs->cr);
96 setbits_le32(&regs->cr, GPT_CR_EN);
/u-boot/drivers/rng/
H A Dstm32_rng.c51 * @cr: Entropy source configuration
59 u32 cr; member in struct:stm32_rng_data
94 u32 cr = readl_relaxed(pdata->base + RNG_CR); local
99 writel_relaxed(cr | RNG_CR_CONDRST, pdata->base + RNG_CR);
100 writel_relaxed(cr & ~RNG_CR_CONDRST, pdata->base + RNG_CR);
255 u32 cr, sr; local
261 cr = readl(pdata->base + RNG_CR);
264 * Keep default RNG configuration if none was specified, that is when conf.cr is set to 0.
266 if (pdata->data->has_cond_reset && pdata->data->cr) {
269 cr
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/u-boot/post/lib_powerpc/
H A Dcpu.c47 ulong cr = 0; local
50 cr |= 0x80000000;
52 cr |= 0x40000000;
54 cr |= 0x20000000;
56 return cr;
H A Drlwimi.c24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
106 ulong cr; local
110 cr = 0;
111 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
113 ret = res == test->res && cr == 0 ? 0 : -1;
123 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
126 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Drlwinm.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
99 ulong cr; local
103 cr = 0;
104 cpu_post_exec_21 (code, & cr, & res, test->op1);
106 ret = res == test->res && cr == 0 ? 0 : -1;
116 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
119 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Dtwox.c27 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
120 ulong cr; local
124 cr = 0;
125 cpu_post_exec_21 (code, & cr, & res, test->op);
127 ret = res == test->res && cr == 0 ? 0 : -1;
137 cpu_post_exec_21 (codecr, & cr, & res, test->op);
140 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Dtwo.c27 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
120 ulong cr; local
124 cr = 0;
125 cpu_post_exec_21 (code, & cr, & res, test->op);
127 ret = res == test->res && cr == 0 ? 0 : -1;
137 cpu_post_exec_21 (codecr, & cr, & res, test->op);
140 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Drlwnm.c24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
109 ulong cr; local
113 cr = 0;
114 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
116 ret = res == test->res && cr == 0 ? 0 : -1;
126 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
129 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Dsrawi.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
100 ulong cr; local
104 cr = 0;
105 cpu_post_exec_21 (code, & cr, & res, test->op1);
107 ret = res == test->res && cr == 0 ? 0 : -1;
117 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
120 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Dcr.c50 ulong cr; member in struct:cpu_post_cr_s2
65 ulong cr; member in struct:cpu_post_cr_s3
88 ulong cr; member in struct:cpu_post_cr_s4
237 ulong cr = cpu_post_cr_table1[i]; local
247 cpu_post_exec_11 (code, &res, cr);
249 ret = res == cr ? 0 : -1;
266 ASM_MCRXR(test->cr),
274 ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ?
296 cpu_post_exec_11 (code, &res, test->cr);
319 cpu_post_exec_11 (code, &res, test->cr);
[all...]
H A Dthreei.c26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
97 ulong cr; local
99 cr = 0;
100 cpu_post_exec_21 (code, & cr, & res, test->op1);
102 ret = res == test->res && cr == 0 ? 0 : -1;
H A Dandi.c24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
83 ulong cr; local
85 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
88 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
H A Dcmp.c35 ulong cr; member in struct:cpu_post_cmp_s
95 ASM_2C(test->cmd, test->cr, 3, 4),
103 ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1;
/u-boot/arch/arm/mach-at91/arm920t/
H A Dreset.c36 writel(AT91_ST_CR_WDRST, &st->cr);
/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dreset.c25 , &rstc->cr);
/u-boot/drivers/mtd/
H A Dstm32_flash.c27 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
102 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
105 setbits_le32(&STM32_FLASH->cr,
108 setbits_le32(&STM32_FLASH->cr,
114 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
115 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
120 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
136 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
147 clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
H A Dstm32_flash.h6 u32 cr; member in struct:stm32_flash_regs
/u-boot/drivers/misc/
H A Dmicrochip_flexcom.c16 u32 cr; member in struct:microchip_flexcom_regs
49 writel(plat->flexcom_mode, &plat->regs->cr);
/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_dbu.h16 u32 cr; /* Control Register WO */ member in struct:at91_dbu
H A Dat91_st.h11 u32 cr; member in struct:at91_st
/u-boot/include/faraday/
H A Dfttmr010.h26 unsigned int cr; /* 0x30 */ member in struct:fttmr010

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