Searched refs:clk_ctrl (Results 1 - 6 of 6) sorted by relevance
/u-boot/drivers/clk/ |
H A D | clk_zynq.c | 104 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) argument 106 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; 119 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) argument 121 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; 136 u32 clk_ctrl, reset, pwrdwn, mul, bypass; local 138 clk_ctrl = readl(zynq_clk_get_register(id)); 140 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; 141 pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; 145 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; 149 mul = (clk_ctrl 157 u32 clk_ctrl, srcsel; local 174 u32 clk_621, clk_ctrl, div; local 206 u32 clk_ctrl, div; local 218 u32 clk_ctrl, div; local 230 u32 clk_ctrl, div0, div1; local 246 u32 clk_ctrl, div0; local 321 u32 clk_ctrl, div0 = 0, div1 = 0; local [all...] |
H A D | clk_zynqmp.c | 345 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, argument 352 src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >> 355 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> 376 u32 clk_ctrl, reset, mul; local 380 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl); 386 if (clk_ctrl & PLLCTRL_BYPASS_MASK) 387 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0); 389 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1); 391 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; 392 if (reset && !(clk_ctrl 408 u32 clk_ctrl, div, srcsel; local 432 u32 clk_ctrl, div, srcsel; local 456 u32 clk_ctrl, srcsel; local 480 u32 clk_ctrl, div0, srcsel; local 520 u32 clk_ctrl, div0, srcsel; local 627 u32 clk_ctrl, div0 = 0, div1 = 0; local 824 u32 reg, clk_ctrl, clkact_shift, mask; local [all...] |
/u-boot/arch/mips/mach-ath79/qca956x/ |
H A D | clk.c | 313 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl; local 367 clk_ctrl = readl(regs + QCA956X_PLL_CLK_CTRL_REG); 369 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & 372 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) 374 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) 379 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & 382 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) 384 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) 389 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & 392 if (clk_ctrl [all...] |
/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 386 u32 clk_ctrl; local 395 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 | 401 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; 402 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); 408 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) | 412 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT; 414 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT; 416 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl);
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/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
H A D | fsl_lsch3_speed.c | 31 struct ccsr_clk_ctrl __iomem *clk_ctrl = local 119 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
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/u-boot/drivers/spi/ |
H A D | ti_qspi.c | 83 u32 clk_ctrl; member in struct:ti_qspi_regs 129 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, 130 &priv->base->clk_ctrl); 132 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
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