#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1de46d91 |
|
31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_NUM_CC_PLLS to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
|
14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
efb5dab7 |
|
21-Aug-2021 |
Tom Rini <trini@konsulko.com> |
nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1de46d91 |
|
31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_NUM_CC_PLLS to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
|
14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
efb5dab7 |
|
21-Aug-2021 |
Tom Rini <trini@konsulko.com> |
nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
1de46d91 |
|
31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_NUM_CC_PLLS to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
|
14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
efb5dab7 |
|
21-Aug-2021 |
Tom Rini <trini@konsulko.com> |
nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
1de46d91 |
|
31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Convert CONFIG_SYS_FSL_NUM_CC_PLLS to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2f8a6db5 |
|
14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
efb5dab7 |
|
21-Aug-2021 |
Tom Rini <trini@konsulko.com> |
nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
2f8a6db5 |
|
14-Dec-2021 |
Tom Rini <trini@konsulko.com> |
Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
efb5dab7 |
|
21-Aug-2021 |
Tom Rini <trini@konsulko.com> |
nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
efb5dab7 |
|
21-Aug-2021 |
Tom Rini <trini@konsulko.com> |
nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
3a187cff |
|
29-Oct-2020 |
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> |
armv8: lx2162a: Add Soc changes to support LX2162A LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
d96c2604 |
|
28-Dec-2019 |
Simon Glass <sjg@chromium.org> |
common: Move clock functions into a new file These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f1bce084 |
|
19-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b5981474 |
|
14-Nov-2019 |
Simon Glass <sjg@chromium.org> |
common: Move some CPU functions out of common.h These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
d3eb317e |
|
12-Nov-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
arm: drop eSDHC clock getting in mxc_get_clock() for layerscape Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
065ee175 |
|
21-Oct-2019 |
Michael Walle <michael@walle.cc> |
armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
24cb6f22 |
|
16-Jul-2019 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
fsl-layerscape: Add fsl_esdhc peripheral clock support Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
087bfe67 |
|
22-May-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller |
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com> |
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
0fdf6967 |
|
25-Sep-2018 |
Yinbo Zhu <yinbo.zhu@nxp.com> |
armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8e63ed51 |
|
02-Feb-2017 |
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
arch: arm: update the IFC IP input clock IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3564208e |
|
10-Jan-2017 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8/fsl-lsch3: consolidate the clock system initialization This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
1cc0a9f4 |
|
04-May-2016 |
Robert P. J. Day <rpjday@crashcourse.ca> |
Fix various typos, scattered over the code. Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
|
#
3c1d218a |
|
04-Apr-2016 |
York Sun <york.sun@nxp.com> |
armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
44937214 |
|
09-Nov-2015 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
armv8: LS2080A: Rename LS2085A to reflect LS2080A LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
|
#
9f3183d2 |
|
26-Oct-2015 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
|