Searched refs:ccm_anatop (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/thermal/
H A Dimx_thermal.c145 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) local
166 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr);
167 writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set);
170 reg = readl(&ccm_anatop->tempsense1);
173 writel(reg, &ccm_anatop->tempsense1);
175 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr);
176 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
177 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
180 while ((readl(&ccm_anatop->tempsense1) &
183 reg = readl(&ccm_anatop
[all...]
/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c22 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) variable in typeref:struct:mxc_ccm_anatop_reg
119 reg = readl(&ccm_anatop->pll_arm);
133 reg = readl(&ccm_anatop->pll_480);
148 reg = readl(&ccm_anatop->pll_enet);
159 reg = readl(&ccm_anatop->pll_ddr);
164 num = ccm_anatop->pll_ddr_num;
165 denom = ccm_anatop->pll_ddr_denom;
192 reg = readl(&ccm_anatop->pll_480);
212 reg = readl(&ccm_anatop->pfd_480a);
221 reg = readl(&ccm_anatop
[all...]
H A Dsoc.c154 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) local
156 u32 reg = readl(&ccm_anatop->digprog);

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