| /u-boot/arch/arm/mach-rockchip/ |
| H A D | cpu-info.c | 18 char *cause = NULL; local
21 return cause;
25 cause = "POR";
29 cause = "RST";
33 cause = "THERMAL";
37 cause = "WDOG";
40 cause = "unknown reset";
43 return cause;
49 char *cause = get_reset_cause(); local
52 printf("Reset cause
[all...] |
| /u-boot/arch/arm/cpu/armv7/vf610/ |
| H A D | generic.c | 290 u32 cause; local
293 cause = readl(&src_regs->srsr);
294 writel(cause, &src_regs->srsr);
296 if (cause & SRC_SRSR_POR_RST)
298 else if (cause & SRC_SRSR_WDOG_A5)
300 else if (cause & SRC_SRSR_WDOG_M4)
302 else if (cause & SRC_SRSR_JTAG_RST)
304 else if (cause & SRC_SRSR_SW_RST)
306 else if (cause & SRC_SRSR_RESETB)
316 printf("Reset cause
[all...] |
| /u-boot/arch/arm/mach-imx/mx7ulp/ |
| H A D | soc.c | 255 char cause[18]; local
264 printf("Reset cause: %s\n", get_reset_cause(cause));
308 u32 cause1, cause = 0, srs = 0; local
321 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
323 switch (cause) {
331 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
333 switch (cause) {
|
| /u-boot/arch/mips/lib/ |
| H A D | traps.c | 32 unsigned int cause = regs->cp0_cause; local
67 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
68 printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
|
| /u-boot/board/ge/mx53ppd/ |
| H A D | mx53ppd.c | 210 const char *cause; local
216 cause = "WDOG";
218 cause = "POR";
220 env_set("bootcause", cause);
|
| /u-boot/arch/riscv/lib/ |
| H A D | interrupts.c | 188 ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs) argument
195 if (cause == CAUSE_BREAKPOINT &&
218 is_irq = (cause & MCAUSE_INT);
219 irq = (cause & ~MCAUSE_INT);
232 _exit_trap(cause, epc, tval, regs);
236 _exit_trap(cause, epc, tval, regs);
|
| /u-boot/arch/arm/mach-imx/imx8ulp/ |
| H A D | soc.c | 210 u32 cause1, cause = 0, srs = 0; local
220 cause = srs & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
222 switch (cause) {
230 cause = srs & (CMC_SRS_WDG | CMC_SRS_SW |
232 switch (cause) {
265 char cause[18]; local
290 printf("Reset cause: %s\n", get_reset_cause(cause));
|
| /u-boot/board/ge/bx50v3/ |
| H A D | bx50v3.c | 488 const char *cause = "POR"; local
492 cause = "PM_WDOG";
494 env_set("bootcause", cause);
|
| /u-boot/board/ge/b1x5v2/ |
| H A D | b1x5v2.c | 551 const char *cause; local
557 cause = "WDOG";
559 cause = "POR";
561 env_set("bootcause", cause);
|
| /u-boot/drivers/ddr/marvell/a38x/ |
| H A D | xor_regs.h | 100 #define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan)))
|
| /u-boot/arch/arm/cpu/arm1136/mx31/ |
| H A D | generic.c | 189 u32 cause = readl(&ccm->rcsr) & 0x07; local
191 switch (cause) {
216 printf("Reset cause: %s\n", get_reset_cause());
|
| /u-boot/board/bosch/shc/ |
| H A D | board.c | 495 static void hang_bosch(const char *cause, int code) argument
506 puts(cause);
|
| /u-boot/arch/riscv/cpu/ |
| H A D | mtrap.S | 64 csrr a0, MODE_PREFIX(cause)
|
| /u-boot/arch/mips/include/asm/ |
| H A D | mipsregs.h | 220 * R4x00 interrupt enable / cause bits
232 * R4x00 interrupt cause bits
354 * Bitfields and bit numbers in the coprocessor 0 cause register.
837 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
1072 * X the exception cause indicator
2776 __BUILD_SET_C0(cause)
2804 __BUILD_SET_GC0(cause)
|
| /u-boot/drivers/net/ |
| H A D | mvpp2.c | 2670 /* Clear BM cause register */
4038 u32 cause)
4040 int queue = fls(cause) - 1;
4046 u32 cause)
4048 int queue = fls(cause) - 1;
4037 mvpp2_get_rx_queue(struct mvpp2_port *port, u32 cause) argument
4045 mvpp2_get_tx_queue(struct mvpp2_port *port, u32 cause) argument
|