1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6#ifndef _XOR_REGS_h 7#define _XOR_REGS_h 8 9/* 10 * For controllers that have two XOR units, then chans 2 & 3 will be 11 * mapped to channels 0 & 1 of unit 1 12 */ 13#define XOR_UNIT(chan) ((chan) >> 1) 14#define XOR_CHAN(chan) ((chan) & 1) 15 16#define MV_XOR_REGS_OFFSET(unit) (0x60900) 17#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) 18 19/* XOR Engine Control Register Map */ 20#define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) 21#define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 22 (0x10 + ((chan) * 4))) 23#define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 24 (0x20 + ((chan) * 4))) 25 26/* XOR Engine Interrupt Register Map */ 27#define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x30)) 28#define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x40)) 29#define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x50)) 30#define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x60)) 31 32/* XOR Engine Descriptor Register Map */ 33#define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 34 (0x200 + ((chan) * 4))) 35#define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 36 (0x210 + ((chan) * 4))) 37#define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 38 (0x220 + ((chan) * 4))) 39 40/* XOR Engine ECC/Mem_init Register Map */ 41#define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 42 (0x2b0 + ((chan) * 4))) 43#define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 44 (0x2c0 + ((chan) * 4))) 45#define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d0)) 46#define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d4)) 47#define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d8)) 48#define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e0)) 49#define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e4)) 50 51/* XOR Engine Debug Register Map */ 52#define XOR_DEBUG_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x70)) 53 54/* XOR register fileds */ 55 56/* XOR Engine Channel Arbiter Register */ 57#define XECAR_SLICE_OFFS(slice_num) (slice_num) 58#define XECAR_SLICE_MASK(slice_num) (1 << (XECAR_SLICE_OFFS(slice_num))) 59 60/* XOR Engine [0..1] Configuration Registers */ 61#define XEXCR_OPERATION_MODE_OFFS (0) 62#define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) 63#define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) 64#define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) 65#define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) 66#define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) 67#define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) 68 69#define XEXCR_SRC_BURST_LIMIT_OFFS (4) 70#define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) 71#define XEXCR_DST_BURST_LIMIT_OFFS (8) 72#define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) 73#define XEXCR_DRD_RES_SWP_OFFS (12) 74#define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) 75#define XEXCR_DWR_REQ_SWP_OFFS (13) 76#define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) 77#define XEXCR_DES_SWP_OFFS (14) 78#define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) 79#define XEXCR_REG_ACC_PROTECT_OFFS (15) 80#define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) 81 82/* XOR Engine [0..1] Activation Registers */ 83#define XEXACTR_XESTART_OFFS (0) 84#define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) 85#define XEXACTR_XESTOP_OFFS (1) 86#define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) 87#define XEXACTR_XEPAUSE_OFFS (2) 88#define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) 89#define XEXACTR_XERESTART_OFFS (3) 90#define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) 91#define XEXACTR_XESTATUS_OFFS (4) 92#define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) 93#define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) 94#define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) 95#define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) 96 97/* XOR Engine Interrupt Cause Register (XEICR) */ 98#define XEICR_CHAN_OFFS 16 99#define XEICR_CAUSE_OFFS(chan) (chan * XEICR_CHAN_OFFS) 100#define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan))) 101#define XEICR_COMP_MASK_ALL 0x000f000f 102#define XEICR_COMP_MASK(chan) (0x000f << XEICR_CAUSE_OFFS(chan)) 103#define XEICR_ERR_MASK 0x03800380 104 105/* XOR Engine Error Cause Register (XEECR) */ 106#define XEECR_ERR_TYPE_OFFS 0 107#define XEECR_ERR_TYPE_MASK (0x1f << XEECR_ERR_TYPE_OFFS) 108 109/* XOR Engine Error Address Register (XEEAR) */ 110#define XEEAR_ERR_ADDR_OFFS (0) 111#define XEEAR_ERR_ADDR_MASK (0xffffffff << XEEAR_ERR_ADDR_OFFS) 112 113/* XOR Engine [0..1] Next Descriptor Pointer Register */ 114#define XEXNDPR_NEXT_DESC_PTR_OFFS (0) 115#define XEXNDPR_NEXT_DESC_PTR_MASK (0xffffffff << \ 116 XEXNDPR_NEXT_DESC_PTR_OFFS) 117 118/* XOR Engine [0..1] Current Descriptor Pointer Register */ 119#define XEXCDPR_CURRENT_DESC_PTR_OFFS (0) 120#define XEXCDPR_CURRENT_DESC_PTR_MASK (0xffffffff << \ 121 XEXCDPR_CURRENT_DESC_PTR_OFFS) 122 123/* XOR Engine [0..1] Byte Count Register */ 124#define XEXBCR_BYTE_CNT_OFFS (0) 125#define XEXBCR_BYTE_CNT_MASK (0xffffffff << XEXBCR_BYTE_CNT_OFFS) 126 127/* XOR Engine [0..1] Destination Pointer Register */ 128#define XEXDPR_DST_PTR_OFFS (0) 129#define XEXDPR_DST_PTR_MASK (0xffffffff << XEXDPR_DST_PTR_OFFS) 130#define XEXDPR_DST_PTR_XOR_MASK (0x3f) 131#define XEXDPR_DST_PTR_DMA_MASK (0x1f) 132#define XEXDPR_DST_PTR_CRC_MASK (0x1f) 133 134/* XOR Engine[0..1] Block Size Registers */ 135#define XEXBSR_BLOCK_SIZE_OFFS (0) 136#define XEXBSR_BLOCK_SIZE_MASK (0xffffffff << XEXBSR_BLOCK_SIZE_OFFS) 137#define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) 138#define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xffffffff) 139 140/* XOR Engine Timer Mode Control Register (XETMCR) */ 141#define XETMCR_TIMER_EN_OFFS (0) 142#define XETMCR_TIMER_EN_MASK (1 << XETMCR_TIMER_EN_OFFS) 143#define XETMCR_TIMER_EN_ENABLE (1 << XETMCR_TIMER_EN_OFFS) 144#define XETMCR_TIMER_EN_DISABLE (0 << XETMCR_TIMER_EN_OFFS) 145#define XETMCR_SECTION_SIZE_CTRL_OFFS (8) 146#define XETMCR_SECTION_SIZE_CTRL_MASK (0x1f << XETMCR_SECTION_SIZE_CTRL_OFFS) 147#define XETMCR_SECTION_SIZE_MIN_VALUE (7) 148#define XETMCR_SECTION_SIZE_MAX_VALUE (31) 149 150/* XOR Engine Timer Mode Initial Value Register (XETMIVR) */ 151#define XETMIVR_TIMER_INIT_VAL_OFFS (0) 152#define XETMIVR_TIMER_INIT_VAL_MASK (0xffffffff << \ 153 XETMIVR_TIMER_INIT_VAL_OFFS) 154 155/* XOR Engine Timer Mode Current Value Register (XETMCVR) */ 156#define XETMCVR_TIMER_CRNT_VAL_OFFS (0) 157#define XETMCVR_TIMER_CRNT_VAL_MASK (0xffffffff << \ 158 XETMCVR_TIMER_CRNT_VAL_OFFS) 159 160/* XOR Engine Initial Value Register Low (XEIVRL) */ 161#define XEIVRL_INIT_VAL_L_OFFS (0) 162#define XEIVRL_INIT_VAL_L_MASK (0xffffffff << XEIVRL_INIT_VAL_L_OFFS) 163 164/* XOR Engine Initial Value Register High (XEIVRH) */ 165#define XEIVRH_INIT_VAL_H_OFFS (0) 166#define XEIVRH_INIT_VAL_H_MASK (0xffffffff << XEIVRH_INIT_VAL_H_OFFS) 167 168/* XOR Engine Debug Register (XEDBR) */ 169#define XEDBR_PARITY_ERR_INSR_OFFS (0) 170#define XEDBR_PARITY_ERR_INSR_MASK (1 << XEDBR_PARITY_ERR_INSR_OFFS) 171#define XEDBR_XBAR_ERR_INSR_OFFS (1) 172#define XEDBR_XBAR_ERR_INSR_MASK (1 << XEDBR_XBAR_ERR_INSR_OFFS) 173 174/* XOR Engine address decode registers. */ 175/* Maximum address decode windows */ 176#define XOR_MAX_ADDR_DEC_WIN 8 177/* Maximum address arbiter windows */ 178#define XOR_MAX_REMAP_WIN 4 179 180/* XOR Engine Address Decoding Register Map */ 181#define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 182 (0x240 + ((chan) * 4))) 183#define XOR_BASE_ADDR_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 184 (0x250 + ((win_num) * 4))) 185#define XOR_SIZE_MASK_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 186 (0x270 + ((win_num) * 4))) 187#define XOR_HIGH_ADDR_REMAP_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 188 (0x290 + ((win_num) * 4))) 189#define XOR_ADDR_OVRD_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 190 (0x2a0 + ((win_num) * 4))) 191 192/* XOR Engine [0..1] Window Control Registers */ 193#define XEXWCR_WIN_EN_OFFS(win_num) (win_num) 194#define XEXWCR_WIN_EN_MASK(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) 195#define XEXWCR_WIN_EN_ENABLE(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) 196#define XEXWCR_WIN_EN_DISABLE(win_num) (0 << (XEXWCR_WIN_EN_OFFS(win_num))) 197 198#define XEXWCR_WIN_ACC_OFFS(win_num) ((2 * win_num) + 16) 199#define XEXWCR_WIN_ACC_MASK(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num))) 200#define XEXWCR_WIN_ACC_NO_ACC(win_num) (0 << (XEXWCR_WIN_ACC_OFFS(win_num))) 201#define XEXWCR_WIN_ACC_RO(win_num) (1 << (XEXWCR_WIN_ACC_OFFS(win_num))) 202#define XEXWCR_WIN_ACC_RW(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num))) 203 204/* XOR Engine Base Address Registers (XEBARx) */ 205#define XEBARX_TARGET_OFFS (0) 206#define XEBARX_TARGET_MASK (0xf << XEBARX_TARGET_OFFS) 207#define XEBARX_ATTR_OFFS (8) 208#define XEBARX_ATTR_MASK (0xff << XEBARX_ATTR_OFFS) 209#define XEBARX_BASE_OFFS (16) 210#define XEBARX_BASE_MASK (0xffff << XEBARX_BASE_OFFS) 211 212/* XOR Engine Size Mask Registers (XESMRx) */ 213#define XESMRX_SIZE_MASK_OFFS (16) 214#define XESMRX_SIZE_MASK_MASK (0xffff << XESMRX_SIZE_MASK_OFFS) 215#define XOR_WIN_SIZE_ALIGN _64K 216 217/* XOR Engine High Address Remap Register (XEHARRx1) */ 218#define XEHARRX_REMAP_OFFS (0) 219#define XEHARRX_REMAP_MASK (0xffffffff << XEHARRX_REMAP_OFFS) 220 221#define XOR_OVERRIDE_CTRL_REG(chan) (MV_XOR_REGS_BASE(XOR_UNIT(chan)) + \ 222 (0x2a0 + ((XOR_CHAN(chan)) * 4))) 223 224/* XOR Engine [0..1] Address Override Control Register */ 225#define XEXAOCR_OVR_EN_OFFS(target) (3 * target) 226#define XEXAOCR_OVR_EN_MASK(target) (1 << (XEXAOCR_OVR_EN_OFFS(target))) 227#define XEXAOCR_OVR_PTR_OFFS(target) ((3 * target) + 1) 228#define XEXAOCR_OVR_PTR_MASK(target) (3 << (XEXAOCR_OVR_PTR_OFFS(target))) 229#define XEXAOCR_OVR_BAR(win_num, target) (win_num << \ 230 (XEXAOCR_OVR_PTR_OFFS(target))) 231 232/* Maximum address override windows */ 233#define XOR_MAX_OVERRIDE_WIN 4 234 235#endif /* _XOR_REGS_h */ 236