Searched refs:base_reg (Results 1 - 5 of 5) sorted by relevance

/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h16 * @base_reg: controller base address for this bank
23 void *base_reg; member in struct:mvebu_pinctrl_priv
H A Dpinctrl-mvebu.c51 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG,
60 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG,
118 clrsetbits_le32(priv->base_reg + reg_offset,
179 clrsetbits_le32(priv->base_reg + reg_offset,
199 priv->base_reg = dev_read_addr_ptr(dev);
200 if (!priv->base_reg) {
/u-boot/drivers/pinctrl/broadcom/
H A Dpinctrl-bcm283x.c27 u32 *base_reg; member in struct:bcm283x_pinctrl_priv
42 clrsetbits_le32(&priv->base_reg[reg_offset],
52 val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]);
113 priv->base_reg = dev_read_addr_ptr(dev);
114 if (!priv->base_reg) {
/u-boot/arch/arm/mach-tegra/
H A Dclock.c612 u32 base_reg, misc_reg; local
628 base_reg = readl(&pll->pll_base);
630 base_reg = readl(&simple_pll->pll_base);
633 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
634 base_reg |= m << pllinfo->m_shift;
636 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
637 base_reg |= n << pllinfo->n_shift;
639 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
640 base_reg |= p << pllinfo->p_shift;
647 if (base_reg
[all...]
/u-boot/drivers/pci/
H A Dpcie_iproc.c50 #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)

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