Searched refs:bar (Results 1 - 25 of 53) sorted by relevance

123

/u-boot/drivers/power/acpi_pmc/
H A Dpmc_emul.c20 * @bar: Current base address values
24 u32 bar[6]; member in struct:pmc_emul_plat
83 u32 *bar; local
86 bar = &plat->bar[barnum];
88 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
112 u32 *bar; local
115 bar = &plat->bar[barnum];
117 debug("w bar
[all...]
/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dlaw.c29 ecm->bar = start & 0xfffff000;
31 debug("DDR:bar=0x%08x\n", ecm->bar);
46 ecm->bar = start & 0xfffff000;
48 debug("DDR:bar=0x%08x\n", ecm->bar);
H A Dcpu_init.c213 im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM;
220 im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM;
224 im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM;
228 im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM;
/u-boot/test/dm/
H A Dpci_ep.c31 struct pci_bar bar = { local
52 ut_assertok(pci_ep_set_bar(bus, 0, &bar));
55 ut_asserteq_mem(&tmp_bar, &bar, sizeof(bar));
H A Dpci.c254 void *bar; local
271 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0);
272 ut_assertnonnull(bar);
273 *(int *)bar = 2; /* swap upper/lower */
275 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0);
276 ut_assertnonnull(bar);
277 strcpy(bar, "ea TEST");
278 unmap_sysmem(bar);
279 bar = dm_pci_map_bar(swap, PCI_BASE_ADDRESS_1, 0, 0, PCI_REGION_TYPE, 0);
280 ut_assertnonnull(bar);
[all...]
/u-boot/api/
H A Dapi_platform-powerpc.c39 si->bar = gd->bd->bi_bar;
42 si->bar = 0;
/u-boot/arch/x86/cpu/intel_common/
H A Dfast_spi.c50 ulong bar, mmio_base; local
53 pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
54 mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
/u-boot/drivers/misc/
H A Dp2sb_emul.c23 * @bar: Current base address values
27 u32 bar[6]; member in struct:p2sb_emul_plat
88 u32 *bar; local
91 bar = &plat->bar[barnum];
93 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
117 u32 *bar; local
120 bar = &plat->bar[barnum];
122 log_debug("w bar
[all...]
H A Dswap_case.c21 * @bar: Current base address values
25 u32 bar[6]; member in struct:swap_case_plat
144 u32 *bar; local
147 bar = &plat->bar[barnum];
149 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
215 u32 *bar; local
218 bar = &plat->bar[barnum];
220 debug("w bar
[all...]
/u-boot/drivers/pci/
H A Dpcie_layerscape_gen4.c311 int bar, u64 phys)
316 if (bar == 1) {
317 ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
322 ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
324 ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
330 int bar; local
337 for (bar = 0; bar < PF_BAR_NUM; bar++) {
338 ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phy
310 ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf, int bar, u64 phys) argument
354 ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf, int bar, bool vf_bar, bool enable) argument
368 ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf, int bar, bool vf_bar, u64 size) argument
380 ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf, int bar, bool vf_bar, u64 size) argument
391 int bar; local
[all...]
H A Dpci_common.c104 void *pci_map_bar(pci_dev_t pdev, int bar, int flags) argument
110 pci_read_config_dword(pdev, bar, &bar_response);
125 int bar; local
127 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
128 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
134 int bar; local
136 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
137 pci_hose_read_config_dword(hose, dev, bar, &addr);
H A Dpci_auto.c32 int bar, bar_nr = 0; local
65 for (bar = PCI_BASE_ADDRESS_0;
66 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
70 dm_pci_write_config32(dev, bar, 0xffffffff);
71 dm_pci_read_config32(dev, bar, &bar_response);
94 dm_pci_write_config32(dev, bar + 4, 0xffffffff);
95 dm_pci_read_config32(dev, bar + 4,
124 printf("PCI: Failed autoconfig bar %x\n", bar);
[all...]
H A Dpci_auto_common.c37 pci_addr_t *bar, bool supports_64bit)
65 *bar = addr;
69 *bar = (pci_addr_t)-1;
36 pciauto_region_allocate(struct pci_region *res, pci_size_t size, pci_addr_t *bar, bool supports_64bit) argument
H A Dpcie_layerscape_gen4.h49 #define BAR_POS(bar, pf, vf_bar) \
50 ((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
144 #define PAB_PEX_BAR_AMAP(pf, bar) \
145 (0x1ba0 + 0x20 * (pf) + 4 * (bar))
147 #define PAB_EXT_PEX_BAR_AMAP(pf, bar) \
148 (0x84a0 + 0x20 * (pf) + 4 * (bar))
H A Dpcie_layerscape.h57 #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
186 int type, int idx, int bar, u64 phys);
H A Dpcie_layerscape_ep.c36 enum pci_barno bar = ep_bar->barno; local
37 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
42 idx = bar;
51 ls_pcie_atu_inbound_set(pcie, fn, 0, type, idx, bar, bar_phys);
125 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) argument
135 switch (bar) {
/u-boot/drivers/pci_endpoint/
H A Dpcie-cadence-ep.c56 enum pci_barno bar = ep_bar->barno; local
77 if (is_64bits && (bar & 1))
95 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
97 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
100 if (bar < BAR_4) {
102 b = bar;
105 b = bar - BAR_4;
H A Dpcie-cadence.h164 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
165 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
169 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
170 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
182 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
183 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
184 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
185 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
/u-boot/arch/x86/cpu/apollolake/
H A Dcpu_common.c79 static void p2sb_enable_bar(ulong bar) argument
82 pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
/u-boot/include/
H A Dpci_ep.h118 * @bar: bar data
122 struct pci_bar *bar);
128 * @bar: struct to copy data to
129 * @barno: bar number to read
133 struct pci_bar *bar, enum pci_barno barno);
139 * @bar: bar number
143 enum pci_barno bar);
278 * @bar
[all...]
/u-boot/arch/x86/cpu/quark/
H A Dquark.c300 u32 bar; local
303 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
304 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
307 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
308 writel(0x7f, bar + USBD_INT_MASK);
309 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
310 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
/u-boot/drivers/nvme/
H A Dnvme_pci.c32 ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0,
H A Dnvme_apple.c96 ((void __iomem *)dev->bar) + ANS_ASQ_DB;
98 ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_ASQ);
102 ((void __iomem *)dev->bar) + ANS_IOSQ_DB;
104 ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_IOSQ);
141 writel(tail, ((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_INVAL);
142 readl(((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_STAT);
256 priv->ndev.bar = priv->base;
/u-boot/arch/x86/include/asm/
H A Dacpi_table.h98 * @bar: Base address of remapping hardware register-set for this unit
101 u64 bar);
111 * @bar: Base address of mapping
114 void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
/u-boot/drivers/virtio/
H A Dvirtio_pci.h97 __u8 bar; /* Where to find it */ member in struct:virtio_pci_cap
99 __le32 offset; /* Offset within bar */

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