#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8db017c8 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pci: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecc8d425 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
be384160 |
|
09-Nov-2021 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: Fix the LUT and msi-map mismatch issue In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
720620e6 |
|
05-Jan-2021 |
Tom Rini <trini@konsulko.com> |
Merge tag 'v2021.01-rc5' into next Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1255f8bc |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
eac36441 |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
8db017c8 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
pci: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ecc8d425 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
be384160 |
|
09-Nov-2021 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: Fix the LUT and msi-map mismatch issue In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
720620e6 |
|
05-Jan-2021 |
Tom Rini <trini@konsulko.com> |
Merge tag 'v2021.01-rc5' into next Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1255f8bc |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
eac36441 |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
ecc8d425 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
be384160 |
|
09-Nov-2021 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: Fix the LUT and msi-map mismatch issue In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
720620e6 |
|
05-Jan-2021 |
Tom Rini <trini@konsulko.com> |
Merge tag 'v2021.01-rc5' into next Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1255f8bc |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
eac36441 |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
be384160 |
|
09-Nov-2021 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: layerscape: Fix the LUT and msi-map mismatch issue In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
720620e6 |
|
05-Jan-2021 |
Tom Rini <trini@konsulko.com> |
Merge tag 'v2021.01-rc5' into next Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1255f8bc |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
eac36441 |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
401d1c4f |
|
30-Oct-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
720620e6 |
|
05-Jan-2021 |
Tom Rini <trini@konsulko.com> |
Merge tag 'v2021.01-rc5' into next Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
8b85dfc6 |
|
16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1255f8bc |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
eac36441 |
|
28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
#
f7ae49fc |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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720620e6 |
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05-Jan-2021 |
Tom Rini <trini@konsulko.com> |
Merge tag 'v2021.01-rc5' into next Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
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#
8b85dfc6 |
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16-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org> |
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1255f8bc |
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28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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eac36441 |
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28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
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f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c4e72c4a |
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27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
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1d341bc4 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
1255f8bc |
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28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Add size check for config resource resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
eac36441 |
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28-Sep-2020 |
Wasim Khan <wasim.khan@nxp.com> |
pci: ls_pcie_g4: Print pcie controller number starting from 1 Print pcie controller number starting from 1 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
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c4e72c4a |
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27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
f7ae49fc |
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10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
c4e72c4a |
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27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
c4e72c4a |
|
27-Jan-2020 |
Simon Glass <sjg@chromium.org> |
dm: pci: Update the PCI read_config() method to const dev * At present this method uses a non-const udevice pointer, but the call should not modify the device. Use a const pointer. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
1d341bc4 |
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08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
1d341bc4 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
#
07ce19f5 |
|
08-Apr-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |