Searched refs:UPDATE (Results 1 - 4 of 4) sorted by relevance

/u-boot/drivers/power/domain/
H A Dtegra186-power-domain.c15 #define UPDATE BIT(0) macro
26 req.logic_state = UPDATE | on_state;
27 req.sram_state = UPDATE | on_state;
33 req.clock_state = UPDATE;
/u-boot/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c22 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
47 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
48 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
61 #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5)
63 #define REG_PREDIV(x) UPDATE(x, 4, 0)
66 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
69 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
71 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
74 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
76 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(
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H A Dphy-rockchip-inno-hdmi.c20 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
31 #define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4)
32 #define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0)
34 #define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4)
35 #define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0)
43 #define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1)
47 #define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0)
52 #define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4)
54 #define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0)
56 #define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(
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/u-boot/lib/zlib/
H A Dinflate.c149 # define UPDATE(check, buf, len) \ macro
152 # define UPDATE(check, buf, len) adler32(check, buf, len) macro
857 UPDATE(state->check, put - out, out);
919 UPDATE(state->check, strm->next_out - out, out);

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