Searched refs:TTBCR (Results 1 - 2 of 2) sorted by relevance
| /u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 55 /* TTBCR flags */
74 #define TTBCR (TTBCR_SHARED_NON | \ macro
192 asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
193 : : "r" (TTBCR) : "memory");
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| /u-boot/arch/arm/mach-uniphier/arm32/ |
| H A D | lowlevel_init.S | 53 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
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