Searched refs:TEGRA186_CLK_PLLREFE_OUT1 (Results 1 - 9 of 9) sorted by relevance

/u-boot/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dtegra186-clock.h183 * @def TEGRA186_CLK_PLLREFE_OUT1
744 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
796 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
841 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dtegra186-clock.h184 * @def TEGRA186_CLK_PLLREFE_OUT1
745 #define TEGRA186_CLK_PLLREFE_OUT1 262 macro
797 /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
842 * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more

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