Searched refs:SPRN_L2CSR1 (Results 1 - 3 of 3) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S276 mtspr SPRN_L2CSR1,r3
H A Dcpu_init.c623 mtspr(SPRN_L2CSR1, (32 + 1));
/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h518 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ macro
736 #define L2CSR1 SPRN_L2CSR1

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