Searched refs:SDRAM_CS_SIZE (Results 1 - 11 of 11) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_sdram.c510 cs_num = (src / (1 + SDRAM_CS_SIZE));
513 channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
517 cs_num = (dst / (1 + SDRAM_CS_SIZE));
521 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
523 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
H A Dddr3_init.c175 reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
179 reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000);
250 reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
254 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000;
H A Dddr3_axp.h25 #define SDRAM_CS_SIZE 0xFFFFFFF macro
27 #define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1) macro
H A Dddr3_dqs.c338 sdram_offset = cs_count * (SDRAM_CS_SIZE + 1);
980 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS +
1136 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS;
1344 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) +
1359 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) +
H A Dddr3_read_leveling.c457 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS;
811 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS;
H A Dddr3_pbs.c1569 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) +
1579 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) +
H A Dddr3_write_leveling.c266 tmp_count * (SDRAM_CS_SIZE + 1) +
/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_plat.h17 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */ macro
H A Dmv_ddr4_training_leveling.c180 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern);
H A Dmv_ddr_plat.c1310 reg |= (SDRAM_CS_SIZE & 0xffff0000);
1314 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) &
H A Dddr3_training_leveling.c1391 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern));

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