Searched refs:REG_TRAINING_WL_CS_MASK (Results 1 - 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h317 #define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC macro
H A Dddr3_write_leveling.c1180 reg = (reg_read(REG_TRAINING_WL_ADDR) & REG_TRAINING_WL_CS_MASK) | cs;

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