Searched refs:REG_TRAINING_WL_1TO1 (Results 1 - 2 of 2) sorted by relevance
| /u-boot/drivers/ddr/marvell/axp/ | ||
| H A D | ddr3_axp.h | 321 #define REG_TRAINING_WL_1TO1 0x50 macro |
| H A D | ddr3_write_leveling.c | 1195 REG_TRAINING_WL_RATIO_MASK) | REG_TRAINING_WL_1TO1; 1241 REG_TRAINING_WL_1TO1; |
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