Searched refs:REG_TRAINING_DEBUG_3_OFFS (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c519 reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
520 reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */
521 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
522 reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */
523 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
524 reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
525 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
526 reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
H A Dddr3_read_leveling.c663 REG_TRAINING_DEBUG_3_OFFS));
719 add = (add >> (phase_min * REG_TRAINING_DEBUG_3_OFFS));
1066 REG_TRAINING_DEBUG_3_OFFS);
1192 add = (add >> phase_min * REG_TRAINING_DEBUG_3_OFFS);
H A Dddr3_axp.h249 #define REG_TRAINING_DEBUG_3_OFFS 3 macro

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