Searched refs:REG_SDRAM_CONFIG_ADDR (Results 1 - 6 of 6) sorted by relevance
/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_dfs.c | 379 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK); 382 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); 388 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK); 391 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); 664 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK); 667 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); 669 reg = reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK; 672 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); 1039 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & 1042 tmp = reg_read(REG_SDRAM_CONFIG_ADDR) | [all...] |
H A D | ddr3_init.c | 86 debug_print_reg(REG_SDRAM_CONFIG_ADDR); 477 reg = reg_read(REG_SDRAM_CONFIG_ADDR); 479 reg_write(REG_SDRAM_CONFIG_ADDR, reg); 499 reg = reg_read(REG_SDRAM_CONFIG_ADDR); 647 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & 649 reg_write(REG_SDRAM_CONFIG_ADDR, reg); 665 reg = reg_read(REG_SDRAM_CONFIG_ADDR); 667 reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
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H A D | ddr3_hw_training.c | 107 reg = reg_read(REG_SDRAM_CONFIG_ADDR); 111 reg_write(REG_SDRAM_CONFIG_ADDR, reg); 116 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
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H A D | ddr3_axp.h | 83 #define REG_SDRAM_CONFIG_ADDR 0x1400 macro
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H A D | ddr3_spd.c | 726 REG_SDRAM_CONFIG_ADDR, REG_SDRAM_CONFIG_ECC_OFFS, 0x1, 0, 0); 770 stat_val = ddr3_get_static_mc_value(REG_SDRAM_CONFIG_ADDR, 0, 788 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
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/u-boot/arch/arm/mach-mvebu/ |
H A D | dram.c | 180 temp = reg_read(REG_SDRAM_CONFIG_ADDR); 182 reg_write(REG_SDRAM_CONFIG_ADDR, temp); 210 temp = reg_read(REG_SDRAM_CONFIG_ADDR); 212 reg_write(REG_SDRAM_CONFIG_ADDR, temp); 217 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) 228 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
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