Searched refs:REG_READ_DATA_READY_DELAYS_ADDR (Results 1 - 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c152 reg_read(REG_READ_DATA_READY_DELAYS_ADDR) &
228 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
240 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
667 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
672 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
723 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
727 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
1069 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
1074 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
1196 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
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H A Dddr3_dfs.c715 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
719 dfs_reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
1516 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
1521 dfs_reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);
H A Dddr3_hw_training.c770 *sdram_offset = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
859 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, val); /* reg 0x153c */
H A Dddr3_axp.h204 #define REG_READ_DATA_READY_DELAYS_ADDR 0x153C macro
H A Dddr3_init.c115 debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR);
H A Dddr3_spd.c1065 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);

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