Searched refs:REG_PHY_REGISTRY_FILE_ACCESS_ADDR (Results 1 - 5 of 5) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c564 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
566 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
569 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
585 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
587 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
590 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
605 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
608 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
611 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
615 return reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR); /*
[all...]
H A Dddr3_init.c799 REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
801 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
896 REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
898 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
H A Dddr3_axp.h305 #define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0 macro
H A Dddr3_write_leveling.c1359 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
1361 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
1364 reg = (reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR)) &
H A Dddr3_pbs.c1519 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
1521 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &

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