Searched refs:REG_PHY_CS_OFFS (Results 1 - 4 of 4) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c558 reg |= ((0x4 * cs + mode) << REG_PHY_CS_OFFS);
582 reg |= ((0x4 * cs + mode + 1) << REG_PHY_CS_OFFS);
604 ((0x4 * cs + mode) << REG_PHY_CS_OFFS);
826 reg = (val >> REG_PHY_CS_OFFS) & 0x3F; /*read the phy address */
H A Dddr3_axp.h311 #define REG_PHY_CS_OFFS 16 macro
H A Dddr3_write_leveling.c1357 reg |= (reg_addr << REG_PHY_CS_OFFS);
H A Dddr3_pbs.c1517 reg |= ((0x4 * cs + PUP_WL_MODE) << REG_PHY_CS_OFFS);

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