Searched refs:REG_DRAM_TRAINING_SHADOW_ADDR (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c91 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) |
93 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg);
97 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) &
514 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) |
516 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg);
520 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) &
H A Dddr3_read_leveling.c79 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) |
81 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg);
85 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) &
90 if (reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) &
H A Dddr3_axp.h210 #define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488 macro

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