Searched refs:REG_DRAM_TRAINING_RL_OFFS (Results 1 - 5 of 5) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_sdram.c643 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
664 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
H A Dddr3_hw_training.c928 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
943 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
H A Dddr3_axp.h216 #define REG_DRAM_TRAINING_RL_OFFS 6 macro
H A Dddr3_pbs.c676 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
694 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
H A Dddr3_read_leveling.c70 reg = 1 << REG_DRAM_TRAINING_RL_OFFS;

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