Searched refs:REG_DRAM_TRAINING_CS_OFFS (Results 1 - 4 of 4) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c667 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) |
670 reg = (0x1 << REG_DRAM_TRAINING_CS_OFFS) |
H A Dddr3_axp.h219 #define REG_DRAM_TRAINING_CS_OFFS 20 macro
H A Dddr3_write_leveling.c88 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS));
511 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS));
H A Dddr3_read_leveling.c75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS);
197 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) |

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