Searched refs:REG_DRAM_TRAINING_AUTO_OFFS (Results 1 - 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c92 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
98 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
227 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS);
515 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
521 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
H A Dddr3_hw_training.c633 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS);
674 reg |= (1 << REG_DRAM_TRAINING_AUTO_OFFS);
H A Dddr3_axp.h224 #define REG_DRAM_TRAINING_AUTO_OFFS 31 macro
H A Dddr3_read_leveling.c80 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
86 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
198 (1 << REG_DRAM_TRAINING_AUTO_OFFS);
H A Dddr3_dqs.c147 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS);
229 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS);
H A Dddr3_pbs.c116 reg = 1 << REG_DRAM_TRAINING_AUTO_OFFS;
559 reg = 1 << REG_DRAM_TRAINING_AUTO_OFFS;

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