Searched refs:REG_DRAM_TRAINING_ADDR (Results 1 - 7 of 7) sorted by relevance
/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_hw_training.c | 634 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 676 reg_write(REG_DRAM_TRAINING_ADDR, reg); 681 if (reg_read(REG_DRAM_TRAINING_ADDR) & 925 reg = reg_read(REG_DRAM_TRAINING_ADDR); 929 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 941 reg = reg_read(REG_DRAM_TRAINING_ADDR); 944 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */
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H A D | ddr3_sdram.c | 641 reg = reg_read(REG_DRAM_TRAINING_ADDR); 646 reg_write(REG_DRAM_TRAINING_ADDR, reg); 661 reg = reg_read(REG_DRAM_TRAINING_ADDR); 667 reg_write(REG_DRAM_TRAINING_ADDR, reg);
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H A D | ddr3_write_leveling.c | 89 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 101 reg = reg_read(REG_DRAM_TRAINING_ADDR); 228 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 512 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 524 reg = reg_read(REG_DRAM_TRAINING_ADDR); 634 reg_write(REG_DRAM_TRAINING_ADDR, 0);
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H A D | ddr3_pbs.c | 117 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 560 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 674 reg = reg_read(REG_DRAM_TRAINING_ADDR); 678 reg_write(REG_DRAM_TRAINING_ADDR, reg); 692 reg = reg_read(REG_DRAM_TRAINING_ADDR); 696 reg_write(REG_DRAM_TRAINING_ADDR, reg);
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H A D | ddr3_axp.h | 211 #define REG_DRAM_TRAINING_ADDR 0x15B0 macro
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H A D | ddr3_read_leveling.c | 77 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 199 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 315 reg_write(REG_DRAM_TRAINING_ADDR, 0); /* 0x15B0 - Training Register */
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H A D | ddr3_dqs.c | 148 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ 230 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */
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