Searched refs:REG_DRAM_TRAINING_2_WL_MODE_OFFS (Results 1 - 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c715 ~(1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS);
826 reg |= (1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS);
950 ~(1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS);
1058 reg |= (1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS);
H A Dddr3_axp.h237 #define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 macro

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