Searched refs:REG_DRAM_TRAINING_2_SW_OVRD_OFFS (Results 1 - 7 of 7) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c221 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
453 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
707 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
833 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
942 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
1065 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
H A Dddr3_pbs.c110 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
383 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
553 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
682 + (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
895 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
H A Dddr3_hw_training.c627 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
646 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
933 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
H A Dddr3_dqs.c140 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
195 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
222 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
275 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
H A Dddr3_axp.h239 #define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0 macro
H A Dddr3_sdram.c650 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
H A Dddr3_read_leveling.c190 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
320 ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);

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