Searched refs:REG_DRAM_TRAINING_2_ECC_MUX_OFFS (Results 1 - 5 of 5) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dqs.c160 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
162 ecc << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
189 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
240 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
242 ecc << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
269 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
H A Dddr3_pbs.c161 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
163 REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
287 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
603 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
605 REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
800 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
H A Dddr3_axp.h238 #define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1 macro
H A Dddr3_write_leveling.c255 REG_DRAM_TRAINING_2_ECC_MUX_OFFS));
259 REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
404 REG_DRAM_TRAINING_2_ECC_MUX_OFFS));
H A Dddr3_read_leveling.c209 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
211 ecc << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);
311 ~(1 << REG_DRAM_TRAINING_2_ECC_MUX_OFFS);

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