Searched refs:REG_DRAM_TRAINING_2_ADDR (Results 1 - 7 of 7) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c220 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
225 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
253 (reg_read(REG_DRAM_TRAINING_2_ADDR)
260 reg_write(REG_DRAM_TRAINING_2_ADDR,
402 (reg_read(REG_DRAM_TRAINING_2_ADDR)
405 reg_write(REG_DRAM_TRAINING_2_ADDR,
452 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
455 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
706 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
710 reg_write(REG_DRAM_TRAINING_2_ADDR, re
[all...]
H A Dddr3_read_leveling.c189 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
194 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
208 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
212 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
299 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
302 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
305 reg = (reg_read(REG_DRAM_TRAINING_2_ADDR)) &
310 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
312 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
319 reg = reg_read(REG_DRAM_TRAINING_2_ADDR)
[all...]
H A Dddr3_pbs.c109 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
113 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
160 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
164 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
286 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
288 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
382 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
385 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
552 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
556 reg_write(REG_DRAM_TRAINING_2_ADDR, re
[all...]
H A Dddr3_dqs.c139 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
144 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
159 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
163 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
188 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
190 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
194 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
197 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
221 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
226 reg_write(REG_DRAM_TRAINING_2_ADDR, re
[all...]
H A Dddr3_hw_training.c626 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
631 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
645 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
648 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
931 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
937 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
H A Dddr3_sdram.c648 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
654 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
657 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
H A Dddr3_axp.h233 #define REG_DRAM_TRAINING_2_ADDR 0x15B8 macro

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