Searched refs:REG_DDR3_MR2_CWL_OFFS (Results 1 - 4 of 4) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c483 & ~(REG_DDR3_MR2_CWL_MASK << REG_DDR3_MR2_CWL_OFFS);
485 reg |= ((0x1) << REG_DDR3_MR2_CWL_OFFS);
1181 ~(REG_DDR3_MR2_CWL_MASK << REG_DDR3_MR2_CWL_OFFS);
1183 reg |= ((0) << REG_DDR3_MR2_CWL_OFFS);
1185 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS);
1497 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS;
H A Dddr3_hw_training.c141 reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
143 reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
H A Dddr3_axp.h279 #define REG_DDR3_MR2_CWL_OFFS 3 macro
H A Dddr3_spd.c1121 reg = ((cwl - 5) << REG_DDR3_MR2_CWL_OFFS);

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