Searched refs:REG_DDR3_MR2_CWL_MASK (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h280 #define REG_DDR3_MR2_CWL_MASK 0x7 macro
H A Dddr3_dfs.c483 & ~(REG_DDR3_MR2_CWL_MASK << REG_DDR3_MR2_CWL_OFFS);
1181 ~(REG_DDR3_MR2_CWL_MASK << REG_DDR3_MR2_CWL_OFFS);
H A Dddr3_hw_training.c146 reg &= REG_DDR3_MR2_CWL_MASK;

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