Searched refs:REG_DDR3_MR1_WL_ENA (Results 1 - 1 of 1) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h274 #define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */ macro

Completed in 83 milliseconds