Searched refs:REG_DDR3_MR1_OUTBUF_WL_MASK (Results 1 - 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c748 REG_DDR3_MR1_OUTBUF_WL_MASK;
804 REG_DDR3_MR1_OUTBUF_WL_MASK;
842 reg &= REG_DDR3_MR1_OUTBUF_WL_MASK;
985 REG_DDR3_MR1_OUTBUF_WL_MASK;
1036 REG_DDR3_MR1_OUTBUF_WL_MASK;
1074 reg &= REG_DDR3_MR1_OUTBUF_WL_MASK;
H A Dddr3_axp.h271 #define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */ macro

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