Searched refs:REG_DDR3_MR1_ODT_MASK (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c683 REG_DDR3_MR1_ODT_MASK;
750 reg &= REG_DDR3_MR1_ODT_MASK;
841 REG_DDR3_MR1_ODT_MASK;
918 REG_DDR3_MR1_ODT_MASK;
987 reg &= REG_DDR3_MR1_ODT_MASK;
1073 REG_DDR3_MR1_ODT_MASK;
H A Dddr3_axp.h275 #define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB macro
H A Dddr3_spd.c1082 reg = 0x00000044 & REG_DDR3_MR1_ODT_MASK;
1084 reg = 0x00000046 & REG_DDR3_MR1_ODT_MASK;

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