Searched refs:REG_DDR3_MR0_CL_OFFS (Results 1 - 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h257 #define REG_DDR3_MR0_CL_OFFS 2 macro
H A Dddr3_dfs.c475 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS);
1173 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS);

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