Searched refs:PS (Results 1 - 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c360 info->rl_val[cs][idx][PS] = phase;
690 if (dram_info->rl_val[cs][pup][PS] < phase_min)
691 phase_min = dram_info->rl_val[cs][pup][PS];
878 dram_info->rl_val[cs][idx][PS] =
1095 DEBUG_RL_S(", PS: ");
1096 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1);
1111 if (dram_info->rl_val[cs][idx][PS] == 4)
1112 dram_info->rl_val[cs][idx][PS] = 1;
1116 delay_s = dram_info->rl_val[cs][idx][PS] *
1133 delay_s = dram_info->rl_val[cs][idx][PS] *
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H A Dddr3_hw_training.h116 #define PS 2 macro
/u-boot/arch/xtensa/cpu/
H A Dstart.S130 /* Set PS.WOE = 0, PS.EXCM = 0 (for loop), PS.INTLEVEL = EXCM level */
137 wsr a2, PS
198 /* Setup PS, PS.WOE = 1, PS.EXCM = 0, PS.INTLEVEL = EXCM level. */
205 wsr a2, PS
326 * - We currently don't use the user exception vector (PS
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