Searched refs:NUM_TX_DESC (Results 1 - 9 of 9) sorted by relevance

/u-boot/drivers/net/
H A Ddc2114x.c79 #define NUM_TX_DESC 1 /* Number of TX descriptors */ macro
95 struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
315 priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
359 priv->tx_new = (priv->tx_new + 1) % NUM_TX_DESC;
412 for (i = 0; i < NUM_TX_DESC; i++) {
420 priv->tx_ring_size = NUM_TX_DESC;
H A Drtl8169.c87 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ macro
329 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
348 unsigned char *Tx_skbuff[NUM_TX_DESC];
605 int entry = tpc->cur_tx % NUM_TX_DESC;
629 if (entry != (NUM_TX_DESC - 1)) {
781 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
784 for (i = 0; i < NUM_TX_DESC; i++) {
1040 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
H A Dmt7628-eth.c124 #define NUM_TX_DESC 4 macro
416 idx = (idx + 1) % NUM_TX_DESC;
493 for (i = 0; i < NUM_TX_DESC; i++) {
515 writel(NUM_TX_DESC, base + TX_MAX_CNT0);
587 sizeof(*priv->tx_ring) * NUM_TX_DESC));
H A Deepro100.c180 #define NUM_TX_DESC 1 /* Number of TX descriptors */ macro
200 struct eepro100_txfd tx_ring[NUM_TX_DESC];
375 memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
379 (sizeof(*tx_ring) * NUM_TX_DESC));
577 priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
598 priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
636 priv->tx_next = (priv->tx_next + 1) % NUM_TX_DESC;
H A Dmt7620-eth.c267 #define NUM_TX_DESC 64 macro
812 memset(priv->tx_ring, 0, NUM_TX_DESC * sizeof(struct pdma_tx_desc));
814 memset(priv->pkt_buf, 0, (NUM_TX_DESC + NUM_RX_DESC) * PKTSIZE_ALIGN);
821 for (i = 0; i < NUM_TX_DESC; i++) {
836 pdma_write(priv, TX_MAX_CNT0, NUM_TX_DESC);
915 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
969 NUM_TX_DESC * sizeof(struct pdma_tx_desc));
983 (NUM_TX_DESC + NUM_RX_DESC) * PKTSIZE_ALIGN);
H A Drtl8139.c92 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ macro
418 priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC;
H A Dsh_eth.c118 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
199 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
221 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
H A Dmtk_eth.c33 #define NUM_TX_DESC 24 macro
35 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
1562 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size);
1572 for (i = 0; i < NUM_TX_DESC; i++) {
1605 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
1749 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
1826 noncached_alloc(priv->soc->txd_size * NUM_TX_DESC,
H A Dsh_eth.h46 #define NUM_TX_DESC 8 macro

Completed in 148 milliseconds