1// SPDX-License-Identifier: GPL-2.0 2/* 3 * rtl8139.c : U-Boot driver for the RealTek RTL8139 4 * 5 * Masami Komiya (mkomiya@sonare.it) 6 * 7 * Most part is taken from rtl8139.c of etherboot 8 * 9 */ 10 11/* rtl8139.c - etherboot driver for the Realtek 8139 chipset 12 * 13 * ported from the linux driver written by Donald Becker 14 * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 15 * 16 * changes to the original driver: 17 * - removed support for interrupts, switching to polling mode (yuck!) 18 * - removed support for the 8129 chip (external MII) 19 */ 20 21/*********************************************************************/ 22/* Revision History */ 23/*********************************************************************/ 24 25/* 26 * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) 27 * Put in virt_to_bus calls to allow Etherboot relocation. 28 * 29 * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) 30 * Following email from Hyun-Joon Cha, added a disable routine, otherwise 31 * NIC remains live and can crash the kernel later. 32 * 33 * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) 34 * Shuffled things around, removed the leftovers from the 8129 support 35 * that was in the Linux driver and added a bit more 8139 definitions. 36 * Moved the 8K receive buffer to a fixed, available address outside the 37 * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only 38 * way to make room for the Etherboot features that need substantial amounts 39 * of code like the ANSI console support. Currently the buffer is just below 40 * 0x10000, so this even conforms to the tagged boot image specification, 41 * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My 42 * interpretation of this "reserved" is that Etherboot may do whatever it 43 * likes, as long as its environment is kept intact (like the BIOS 44 * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms 45 * were that if Etherboot was left at the boot menu for several minutes, the 46 * first eth_poll failed. Seems like I am the only person who does this. 47 * First of all I fixed the debugging code and then set out for a long bug 48 * hunting session. It took me about a week full time work - poking around 49 * various places in the driver, reading Don Becker's and Jeff Garzik's Linux 50 * driver and even the FreeBSD driver (what a piece of crap!) - and 51 * eventually spotted the nasty thing: the transmit routine was acknowledging 52 * each and every interrupt pending, including the RxOverrun and RxFIFIOver 53 * interrupts. This confused the RTL8139 thoroughly. It destroyed the 54 * Rx ring contents by dumping the 2K FIFO contents right where we wanted to 55 * get the next packet. Oh well, what fun. 56 * 57 * 18 Jan 2000 mdc@thinguin.org (Marty Connor) 58 * Drastically simplified error handling. Basically, if any error 59 * in transmission or reception occurs, the card is reset. 60 * Also, pointed all transmit descriptors to the same buffer to 61 * save buffer space. This should decrease driver size and avoid 62 * corruption because of exceeding 32K during runtime. 63 * 64 * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) 65 * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead 66 * of the RxBufferEmpty flag which often resulted in very bad 67 * transmission performace - below 1kBytes/s. 68 * 69 */ 70 71#include <cpu_func.h> 72#include <dm.h> 73#include <log.h> 74#include <malloc.h> 75#include <net.h> 76#include <netdev.h> 77#include <asm/io.h> 78#include <pci.h> 79#include <linux/bitops.h> 80#include <linux/delay.h> 81#include <linux/types.h> 82 83#define RTL_TIMEOUT 100000 84 85/* PCI Tuning Parameters */ 86/* Threshold is bytes transferred to chip before transmission starts. */ 87#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 88#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ 89#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ 90#define TX_DMA_BURST 4 /* Calculate as 16<<val. */ 91#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ 92#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */ 93#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ 94#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 95 96#define DEBUG_TX 0 /* set to 1 to enable debug code */ 97#define DEBUG_RX 0 /* set to 1 to enable debug code */ 98 99#define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a)) 100#define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a)) 101 102/* Symbolic offsets to registers. */ 103/* Ethernet hardware address. */ 104#define RTL_REG_MAC0 0x00 105/* Multicast filter. */ 106#define RTL_REG_MAR0 0x08 107/* Transmit status (four 32bit registers). */ 108#define RTL_REG_TXSTATUS0 0x10 109/* Tx descriptors (also four 32bit). */ 110#define RTL_REG_TXADDR0 0x20 111#define RTL_REG_RXBUF 0x30 112#define RTL_REG_RXEARLYCNT 0x34 113#define RTL_REG_RXEARLYSTATUS 0x36 114#define RTL_REG_CHIPCMD 0x37 115#define RTL_REG_CHIPCMD_CMDRESET BIT(4) 116#define RTL_REG_CHIPCMD_CMDRXENB BIT(3) 117#define RTL_REG_CHIPCMD_CMDTXENB BIT(2) 118#define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0) 119#define RTL_REG_RXBUFPTR 0x38 120#define RTL_REG_RXBUFADDR 0x3A 121#define RTL_REG_INTRMASK 0x3C 122#define RTL_REG_INTRSTATUS 0x3E 123#define RTL_REG_INTRSTATUS_PCIERR BIT(15) 124#define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14) 125#define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13) 126#define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6) 127#define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5) 128#define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4) 129#define RTL_REG_INTRSTATUS_TXERR BIT(3) 130#define RTL_REG_INTRSTATUS_TXOK BIT(2) 131#define RTL_REG_INTRSTATUS_RXERR BIT(1) 132#define RTL_REG_INTRSTATUS_RXOK BIT(0) 133#define RTL_REG_TXCONFIG 0x40 134#define RTL_REG_RXCONFIG 0x44 135#define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7) 136#define RTL_REG_RXCONFIG_ACCEPTERR BIT(5) 137#define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4) 138#define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3) 139#define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2) 140#define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1) 141#define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0) 142/* general-purpose counter. */ 143#define RTL_REG_TIMER 0x48 144/* 24 bits valid, write clears. */ 145#define RTL_REG_RXMISSED 0x4C 146#define RTL_REG_CFG9346 0x50 147#define RTL_REG_CONFIG0 0x51 148#define RTL_REG_CONFIG1 0x52 149/* intr if gp counter reaches this value */ 150#define RTL_REG_TIMERINTRREG 0x54 151#define RTL_REG_MEDIASTATUS 0x58 152#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7) 153#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6) 154#define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3) 155#define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2) 156#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1) 157#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0) 158#define RTL_REG_CONFIG3 0x59 159#define RTL_REG_MULTIINTR 0x5C 160/* revision of the RTL8139 chip */ 161#define RTL_REG_REVISIONID 0x5E 162#define RTL_REG_TXSUMMARY 0x60 163#define RTL_REG_MII_BMCR 0x62 164#define RTL_REG_MII_BMSR 0x64 165#define RTL_REG_NWAYADVERT 0x66 166#define RTL_REG_NWAYLPAR 0x68 167#define RTL_REG_NWAYEXPANSION 0x6A 168#define RTL_REG_DISCONNECTCNT 0x6C 169#define RTL_REG_FALSECARRIERCNT 0x6E 170#define RTL_REG_NWAYTESTREG 0x70 171/* packet received counter */ 172#define RTL_REG_RXCNT 0x72 173/* chip status and configuration register */ 174#define RTL_REG_CSCR 0x74 175#define RTL_REG_PHYPARM1 0x78 176#define RTL_REG_TWISTERPARM 0x7c 177/* undocumented */ 178#define RTL_REG_PHYPARM2 0x80 179/* 180 * from 0x84 onwards are a number of power management/wakeup frame 181 * definitions we will probably never need to know about. 182 */ 183 184#define RTL_STS_RXMULTICAST BIT(15) 185#define RTL_STS_RXPHYSICAL BIT(14) 186#define RTL_STS_RXBROADCAST BIT(13) 187#define RTL_STS_RXBADSYMBOL BIT(5) 188#define RTL_STS_RXRUNT BIT(4) 189#define RTL_STS_RXTOOLONG BIT(3) 190#define RTL_STS_RXCRCERR BIT(2) 191#define RTL_STS_RXBADALIGN BIT(1) 192#define RTL_STS_RXSTATUSOK BIT(0) 193 194struct rtl8139_priv { 195 struct udevice *devno; 196 unsigned int rxstatus; 197 unsigned int cur_rx; 198 unsigned int cur_tx; 199 unsigned long ioaddr; 200 unsigned char enetaddr[6]; 201}; 202 203/* The RTL8139 can only transmit from a contiguous, aligned memory block. */ 204static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4); 205static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4); 206 207/* Serial EEPROM section. */ 208 209/* EEPROM_Ctrl bits. */ 210#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 211#define EE_CS 0x08 /* EEPROM chip select. */ 212#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 213#define EE_WRITE_0 0x00 214#define EE_WRITE_1 0x02 215#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 216#define EE_ENB (0x80 | EE_CS) 217 218/* The EEPROM commands include the alway-set leading bit. */ 219#define EE_WRITE_CMD 5 220#define EE_READ_CMD 6 221#define EE_ERASE_CMD 7 222 223static void rtl8139_eeprom_delay(struct rtl8139_priv *priv) 224{ 225 /* 226 * Delay between EEPROM clock transitions. 227 * No extra delay is needed with 33MHz PCI, but 66MHz may change this. 228 */ 229 inl(priv->ioaddr + RTL_REG_CFG9346); 230} 231 232static int rtl8139_read_eeprom(struct rtl8139_priv *priv, 233 unsigned int location, unsigned int addr_len) 234{ 235 unsigned int read_cmd = location | (EE_READ_CMD << addr_len); 236 uintptr_t ee_addr = priv->ioaddr + RTL_REG_CFG9346; 237 unsigned int retval = 0; 238 u8 dataval; 239 int i; 240 241 outb(EE_ENB & ~EE_CS, ee_addr); 242 outb(EE_ENB, ee_addr); 243 rtl8139_eeprom_delay(priv); 244 245 /* Shift the read command bits out. */ 246 for (i = 4 + addr_len; i >= 0; i--) { 247 dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0; 248 outb(EE_ENB | dataval, ee_addr); 249 rtl8139_eeprom_delay(priv); 250 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 251 rtl8139_eeprom_delay(priv); 252 } 253 254 outb(EE_ENB, ee_addr); 255 rtl8139_eeprom_delay(priv); 256 257 for (i = 16; i > 0; i--) { 258 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); 259 rtl8139_eeprom_delay(priv); 260 retval <<= 1; 261 retval |= inb(ee_addr) & EE_DATA_READ; 262 outb(EE_ENB, ee_addr); 263 rtl8139_eeprom_delay(priv); 264 } 265 266 /* Terminate the EEPROM access. */ 267 outb(~EE_CS, ee_addr); 268 rtl8139_eeprom_delay(priv); 269 270 return retval; 271} 272 273static const unsigned int rtl8139_rx_config = 274 (RX_BUF_LEN_IDX << 11) | 275 (RX_FIFO_THRESH << 13) | 276 (RX_DMA_BURST << 8); 277 278static void rtl8139_set_rx_mode(struct rtl8139_priv *priv) 279{ 280 /* !IFF_PROMISC */ 281 unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST | 282 RTL_REG_RXCONFIG_ACCEPTMULTICAST | 283 RTL_REG_RXCONFIG_ACCEPTMYPHYS; 284 285 outl(rtl8139_rx_config | rx_mode, priv->ioaddr + RTL_REG_RXCONFIG); 286 287 outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 0); 288 outl(0xffffffff, priv->ioaddr + RTL_REG_MAR0 + 4); 289} 290 291static void rtl8139_hw_reset(struct rtl8139_priv *priv) 292{ 293 u8 reg; 294 int i; 295 296 outb(RTL_REG_CHIPCMD_CMDRESET, priv->ioaddr + RTL_REG_CHIPCMD); 297 298 /* Give the chip 10ms to finish the reset. */ 299 for (i = 0; i < 100; i++) { 300 reg = inb(priv->ioaddr + RTL_REG_CHIPCMD); 301 if (!(reg & RTL_REG_CHIPCMD_CMDRESET)) 302 break; 303 304 udelay(100); 305 } 306} 307 308static void rtl8139_reset(struct rtl8139_priv *priv) 309{ 310 int i; 311 312 priv->cur_rx = 0; 313 priv->cur_tx = 0; 314 315 rtl8139_hw_reset(priv); 316 317 for (i = 0; i < ETH_ALEN; i++) 318 outb(priv->enetaddr[i], priv->ioaddr + RTL_REG_MAC0 + i); 319 320 /* Must enable Tx/Rx before setting transfer thresholds! */ 321 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, 322 priv->ioaddr + RTL_REG_CHIPCMD); 323 324 /* accept no frames yet! */ 325 outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG); 326 outl((TX_DMA_BURST << 8) | 0x03000000, priv->ioaddr + RTL_REG_TXCONFIG); 327 328 /* 329 * The Linux driver changes RTL_REG_CONFIG1 here to use a different 330 * LED pattern for half duplex or full/autodetect duplex (for 331 * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while 332 * for half duplex it uses TX/RX, Link100, Link10). This is messy, 333 * because it doesn't match the inscription on the mounting bracket. 334 * It should not be changed from the configuration EEPROM default, 335 * because the card manufacturer should have set that to match the 336 * card. 337 */ 338 debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring); 339 340 flush_cache((unsigned long)rx_ring, RX_BUF_LEN); 341 outl(phys_to_bus(priv->devno, (int)rx_ring), priv->ioaddr + RTL_REG_RXBUF); 342 343 /* 344 * If we add multicast support, the RTL_REG_MAR0 register would have 345 * to be initialized to 0xffffffffffffffff (two 32 bit accesses). 346 * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and 347 * unicast. 348 */ 349 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, 350 priv->ioaddr + RTL_REG_CHIPCMD); 351 352 outl(rtl8139_rx_config, priv->ioaddr + RTL_REG_RXCONFIG); 353 354 /* Start the chip's Tx and Rx process. */ 355 outl(0, priv->ioaddr + RTL_REG_RXMISSED); 356 357 rtl8139_set_rx_mode(priv); 358 359 /* Disable all known interrupts by setting the interrupt mask. */ 360 outw(0, priv->ioaddr + RTL_REG_INTRMASK); 361} 362 363static int rtl8139_send_common(struct rtl8139_priv *priv, 364 void *packet, int length) 365{ 366 unsigned int len = length; 367 unsigned long txstatus; 368 unsigned int status; 369 int i = 0; 370 371 memcpy(tx_buffer, packet, length); 372 373 debug_cond(DEBUG_TX, "sending %d bytes\n", len); 374 375 /* 376 * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 377 * bytes are sent automatically for the FCS, totalling to 64 bytes). 378 */ 379 while (len < ETH_ZLEN) 380 tx_buffer[len++] = '\0'; 381 382 flush_cache((unsigned long)tx_buffer, length); 383 outl(phys_to_bus(priv->devno, (unsigned long)tx_buffer), 384 priv->ioaddr + RTL_REG_TXADDR0 + priv->cur_tx * 4); 385 outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len, 386 priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4); 387 388 do { 389 status = inw(priv->ioaddr + RTL_REG_INTRSTATUS); 390 /* 391 * Only acknlowledge interrupt sources we can properly 392 * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/ 393 * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the 394 * rtl8139_recv() function. 395 */ 396 status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR | 397 RTL_REG_INTRSTATUS_PCIERR; 398 outw(status, priv->ioaddr + RTL_REG_INTRSTATUS); 399 if (status) 400 break; 401 402 udelay(10); 403 } while (i++ < RTL_TIMEOUT); 404 405 txstatus = inl(priv->ioaddr + RTL_REG_TXSTATUS0 + priv->cur_tx * 4); 406 407 if (!(status & RTL_REG_INTRSTATUS_TXOK)) { 408 debug_cond(DEBUG_TX, 409 "tx timeout/error (%d usecs), status %hX txstatus %lX\n", 410 10 * i, status, txstatus); 411 412 rtl8139_reset(priv); 413 414 return 0; 415 } 416 417 priv->cur_tx = (priv->cur_tx + 1) % NUM_TX_DESC; 418 419 debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n", 420 status, txstatus); 421 422 return length; 423} 424 425static int rtl8139_recv_common(struct rtl8139_priv *priv, unsigned char *rxdata, 426 uchar **packetp) 427{ 428 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER | 429 RTL_REG_INTRSTATUS_RXOVERFLOW | 430 RTL_REG_INTRSTATUS_RXOK; 431 unsigned int rx_size, rx_status; 432 unsigned int ring_offs; 433 int length = 0; 434 435 if (inb(priv->ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) 436 return 0; 437 438 priv->rxstatus = inw(priv->ioaddr + RTL_REG_INTRSTATUS); 439 /* See below for the rest of the interrupt acknowledges. */ 440 outw(priv->rxstatus & ~rxstat, priv->ioaddr + RTL_REG_INTRSTATUS); 441 442 debug_cond(DEBUG_RX, "%s: int %hX ", __func__, priv->rxstatus); 443 444 ring_offs = priv->cur_rx % RX_BUF_LEN; 445 /* ring_offs is guaranteed being 4-byte aligned */ 446 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs)); 447 rx_size = rx_status >> 16; 448 rx_status &= 0xffff; 449 450 if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT | 451 RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR | 452 RTL_STS_RXBADALIGN)) || 453 (rx_size < ETH_ZLEN) || 454 (rx_size > ETH_FRAME_LEN + 4)) { 455 debug("rx error %hX\n", rx_status); 456 /* this clears all interrupts still pending */ 457 rtl8139_reset(priv); 458 return 0; 459 } 460 461 /* Received a good packet */ 462 length = rx_size - 4; /* no one cares about the FCS */ 463 if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) { 464 int semi_count = RX_BUF_LEN - ring_offs - 4; 465 466 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); 467 memcpy(&rxdata[semi_count], rx_ring, 468 rx_size - 4 - semi_count); 469 470 *packetp = rxdata; 471 debug_cond(DEBUG_RX, "rx packet %d+%d bytes", 472 semi_count, rx_size - 4 - semi_count); 473 } else { 474 *packetp = rx_ring + ring_offs + 4; 475 debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4); 476 } 477 478 return length; 479} 480 481static int rtl8139_free_pkt_common(struct rtl8139_priv *priv, unsigned int len) 482{ 483 const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER | 484 RTL_REG_INTRSTATUS_RXOVERFLOW | 485 RTL_REG_INTRSTATUS_RXOK; 486 unsigned int rx_size = len + 4; 487 488 flush_cache((unsigned long)rx_ring, RX_BUF_LEN); 489 490 priv->cur_rx = ROUND(priv->cur_rx + rx_size + 4, 4); 491 outw(priv->cur_rx - 16, priv->ioaddr + RTL_REG_RXBUFPTR); 492 /* 493 * See RTL8139 Programming Guide V0.1 for the official handling of 494 * Rx overflow situations. The document itself contains basically 495 * no usable information, except for a few exception handling rules. 496 */ 497 outw(priv->rxstatus & rxstat, priv->ioaddr + RTL_REG_INTRSTATUS); 498 499 return 0; 500} 501 502static int rtl8139_init_common(struct rtl8139_priv *priv) 503{ 504 u8 reg; 505 506 /* Bring the chip out of low-power mode. */ 507 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1); 508 509 rtl8139_reset(priv); 510 511 reg = inb(priv->ioaddr + RTL_REG_MEDIASTATUS); 512 if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { 513 printf("Cable not connected or other link failure\n"); 514 return -1; 515 } 516 517 return 0; 518} 519 520static void rtl8139_stop_common(struct rtl8139_priv *priv) 521{ 522 rtl8139_hw_reset(priv); 523} 524 525static void rtl8139_get_hwaddr(struct rtl8139_priv *priv) 526{ 527 unsigned short *ap = (unsigned short *)priv->enetaddr; 528 int i, addr_len; 529 530 /* Bring the chip out of low-power mode. */ 531 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1); 532 533 addr_len = rtl8139_read_eeprom(priv, 0, 8) == 0x8129 ? 8 : 6; 534 for (i = 0; i < 3; i++) 535 *ap++ = le16_to_cpu(rtl8139_read_eeprom(priv, i + 7, addr_len)); 536} 537 538static void rtl8139_name(char *str, int card_number) 539{ 540 sprintf(str, "RTL8139#%u", card_number); 541} 542 543static struct pci_device_id supported[] = { 544 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139) }, 545 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139) }, 546 { } 547}; 548 549static int rtl8139_start(struct udevice *dev) 550{ 551 struct eth_pdata *plat = dev_get_plat(dev); 552 struct rtl8139_priv *priv = dev_get_priv(dev); 553 554 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr)); 555 556 return rtl8139_init_common(priv); 557} 558 559static void rtl8139_stop(struct udevice *dev) 560{ 561 struct rtl8139_priv *priv = dev_get_priv(dev); 562 563 rtl8139_stop_common(priv); 564} 565 566static int rtl8139_send(struct udevice *dev, void *packet, int length) 567{ 568 struct rtl8139_priv *priv = dev_get_priv(dev); 569 int ret; 570 571 ret = rtl8139_send_common(priv, packet, length); 572 573 return ret ? 0 : -ETIMEDOUT; 574} 575 576static int rtl8139_recv(struct udevice *dev, int flags, uchar **packetp) 577{ 578 struct rtl8139_priv *priv = dev_get_priv(dev); 579 static unsigned char rxdata[RX_BUF_LEN]; 580 581 return rtl8139_recv_common(priv, rxdata, packetp); 582} 583 584static int rtl8139_free_pkt(struct udevice *dev, uchar *packet, int length) 585{ 586 struct rtl8139_priv *priv = dev_get_priv(dev); 587 588 rtl8139_free_pkt_common(priv, length); 589 590 return 0; 591} 592 593static int rtl8139_write_hwaddr(struct udevice *dev) 594{ 595 struct eth_pdata *plat = dev_get_plat(dev); 596 struct rtl8139_priv *priv = dev_get_priv(dev); 597 598 memcpy(priv->enetaddr, plat->enetaddr, sizeof(plat->enetaddr)); 599 600 rtl8139_reset(priv); 601 602 return 0; 603} 604 605static int rtl8139_read_rom_hwaddr(struct udevice *dev) 606{ 607 struct rtl8139_priv *priv = dev_get_priv(dev); 608 609 rtl8139_get_hwaddr(priv); 610 611 return 0; 612} 613 614static int rtl8139_bind(struct udevice *dev) 615{ 616 static int card_number; 617 char name[16]; 618 619 rtl8139_name(name, card_number++); 620 621 return device_set_name(dev, name); 622} 623 624static int rtl8139_probe(struct udevice *dev) 625{ 626 struct eth_pdata *plat = dev_get_plat(dev); 627 struct rtl8139_priv *priv = dev_get_priv(dev); 628 u32 iobase; 629 630 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase); 631 iobase &= ~0xf; 632 633 debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); 634 635 priv->devno = dev; 636 priv->ioaddr = (unsigned long)bus_to_phys(dev, iobase); 637 638 rtl8139_get_hwaddr(priv); 639 memcpy(plat->enetaddr, priv->enetaddr, sizeof(priv->enetaddr)); 640 641 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x20); 642 643 return 0; 644} 645 646static const struct eth_ops rtl8139_ops = { 647 .start = rtl8139_start, 648 .send = rtl8139_send, 649 .recv = rtl8139_recv, 650 .stop = rtl8139_stop, 651 .free_pkt = rtl8139_free_pkt, 652 .write_hwaddr = rtl8139_write_hwaddr, 653 .read_rom_hwaddr = rtl8139_read_rom_hwaddr, 654}; 655 656U_BOOT_DRIVER(eth_rtl8139) = { 657 .name = "eth_rtl8139", 658 .id = UCLASS_ETH, 659 .bind = rtl8139_bind, 660 .probe = rtl8139_probe, 661 .ops = &rtl8139_ops, 662 .priv_auto = sizeof(struct rtl8139_priv), 663 .plat_auto = sizeof(struct eth_pdata), 664}; 665 666U_BOOT_PCI_DEVICE(eth_rtl8139, supported); 667