Searched refs:MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c393 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
/u-boot/arch/arm/include/asm/arch-mx5/
H A Dcrm_regs.h178 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) macro

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