Searched refs:MD_CTR (Results 1 - 2 of 2) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c38 mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */
/u-boot/arch/powerpc/include/asm/
H A Dmmu.h293 #define MD_CTR 792 /* Data TLB control register */ macro

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