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Searched refs:M0 (Results 1 - 18 of 18) sorted by relevance

/u-boot/board/logicpd/omap3som/
H A D	omap3logic.h	36 * M0 - Mode 0 48 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/ 49 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/ 50 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/ 51 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/ 52 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/ 53 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/ 54 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/ 55 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/ 56 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /*SDRC_D [all...]
/u-boot/board/logicpd/am3517evm/
H A D	am3517evm.h	`29 * M0 - Mode 0 34 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) \ 35 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) \ 36 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) \ 37 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) \ 38 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) \ 39 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) \ 40 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) \ 41 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) \ 42 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) \ [all...]`
/u-boot/board/ti/omap3evm/
H A D	evm.h	45 * M0 - Mode 0 50 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\ 51 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\ 52 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\ 53 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\ 54 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\ 55 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\ 56 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\ 57 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\ 58 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /*SDRC_D [all...]
/u-boot/board/isee/igep00x0/
H A D	igep00x0.h	16 * M0 - Mode 0 20 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /* SDRC_D0 /\ 21 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) / SDRC_D1 /\ 22 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) / SDRC_D2 /\ 23 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) / SDRC_D3 /\ 24 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) / SDRC_D4 /\ 25 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) / SDRC_D5 /\ 26 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) / SDRC_D6 /\ 27 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) / SDRC_D7 /\ 28 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) / SDRC_D [all...]
/u-boot/board/ti/dra7xx/
H A D	mux_data.h	61 {VIN2A_CLK0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 / 62 {VIN2A_HSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE6)}, / vin2a_hsync0.vin2a_hsync0 / 63 {VIN2A_VSYNC0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE9)}, / vin2a_vsync0.vin2a_vsync0 / 64 {VIN2A_D0, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, / vin2a_d0.vin2a_d0 / 65 {VIN2A_D1, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, / vin2a_d1.vin2a_d1 / 66 {VIN2A_D2, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE14)}, / vin2a_d2.vin2a_d2 / 67 {VIN2A_D3, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, / vin2a_d3.vin2a_d3 / 68 {VIN2A_D4, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, / vin2a_d4.vin2a_d4 / 69 {VIN2A_D5, (M0 \| PIN_INPUT_PULLDOWN \| VIRTUAL_MODE8)}, / vin2a_d5.vin2a_d5 */ 70 {VIN2A_D6, (M0 \| PIN_INPUT_PULLDOW [all...]
/u-boot/board/timll/devkit8000/
H A D	devkit8000.h	28 * M0 - Mode 0 34 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\ 35 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\ 36 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\ 37 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\ 38 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\ 39 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\ 40 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\ 41 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\ 42 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /*SDRC_D [all...]
/u-boot/board/ti/panda/
H A D	panda_mux_data.h	27 {SDMMC1_CLK, (PTU \| OFF_EN \| OFF_OUT_PTD \| M0)}, /* sdmmc1_clk / 28 {SDMMC1_CMD, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_cmd / 29 {SDMMC1_DAT0, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat0 / 30 {SDMMC1_DAT1, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat1 / 31 {SDMMC1_DAT2, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat2 / 32 {SDMMC1_DAT3, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat3 / 33 {SDMMC1_DAT4, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat4 / 34 {SDMMC1_DAT5, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat5 / 35 {SDMMC1_DAT6, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat6 / 36 {SDMMC1_DAT7, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat [all...]
/u-boot/board/lg/sniper/
H A D	sniper.h	15 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /* sdrc_d0 /\ 16 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) / sdrc_d1 /\ 17 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) / sdrc_d2 /\ 18 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) / sdrc_d3 /\ 19 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) / sdrc_d4 /\ 20 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) / sdrc_d5 /\ 21 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) / sdrc_d6 /\ 22 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) / sdrc_d7 /\ 23 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) / sdrc_d8 /\ 24 MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)) / sdrc_d [all...]
/u-boot/board/ti/am57xx/
H A D	mux_data.h	116 {MDIO_MCLK, (M0 \| PIN_OUTPUT \| SLEWCONTROL)}, /* mdio_mclk.mdio_mclk / 117 {MDIO_D, (M0 \| PIN_INPUT \| SLEWCONTROL)}, / mdio_d.mdio_d / 121 {RGMII0_TXC, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, / rgmii0_txc.rgmii0_txc / 122 {RGMII0_TXCTL, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, / rgmii0_txctl.rgmii0_txctl / 123 {RGMII0_TXD3, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, / rgmii0_txd3.rgmii0_txd3 / 124 {RGMII0_TXD2, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, / rgmii0_txd2.rgmii0_txd2 / 125 {RGMII0_TXD1, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, / rgmii0_txd1.rgmii0_txd1 / 126 {RGMII0_TXD0, (M0 \| PIN_OUTPUT \| MANUAL_MODE)}, / rgmii0_txd0.rgmii0_txd0 / 127 {RGMII0_RXC, (M0 \| PIN_INPUT \| MANUAL_MODE)}, / rgmii0_rxc.rgmii0_rxc */ 128 {RGMII0_RXCTL, (M0 \| PIN_INPU [all...]
/u-boot/board/ti/sdp4430/
H A D	sdp4430_mux_data.h	26 {SDMMC1_CLK, (PTU \| OFF_EN \| OFF_OUT_PTD \| M0)}, /* sdmmc1_clk / 27 {SDMMC1_CMD, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_cmd / 28 {SDMMC1_DAT0, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat0 / 29 {SDMMC1_DAT1, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat1 / 30 {SDMMC1_DAT2, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat2 / 31 {SDMMC1_DAT3, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat3 / 32 {SDMMC1_DAT4, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat4 / 33 {SDMMC1_DAT5, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat5 / 34 {SDMMC1_DAT6, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat6 / 35 {SDMMC1_DAT7, (PTU \| IEN \| OFF_EN \| OFF_PD \| OFF_IN \| M0)}, / sdmmc1_dat [all...]
/u-boot/board/beagle/beagle/
H A D	beagle.h	35 * M0 - Mode 0 40 MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) /SDRC_D0/\ 41 MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) /SDRC_D1/\ 42 MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) /SDRC_D2/\ 43 MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) /SDRC_D3/\ 44 MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) /SDRC_D4/\ 45 MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) /SDRC_D5/\ 46 MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) /SDRC_D6/\ 47 MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) /SDRC_D7/\ 48 MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) /*SDRC_D [all...]
/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A D	tie-asm.h	`81 rsr \at1, M0 // MAC16 option 146 wsr \at1, M0 // MAC16 option`
/u-boot/arch/xtensa/include/asm/arch-de212/
H A D	tie-asm.h	`74 rsr.M0 \at1 // MAC16 option 129 wsr.M0 \at1 // MAC16 option`
/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A D	tie-asm.h	`46 rsr \at1, M0 // MAC16 registers 89 wsr \at1, M0 // MAC16 registers`
/u-boot/arch/x86/include/asm/arch-braswell/
H A D	gpio.h	`14 M0, enumerator in enum:mode_list`
/u-boot/arch/arm/include/asm/arch-omap4/
H A D	mux_omap4.h	`47 #define M0 0 macro`
/u-boot/arch/arm/include/asm/arch-omap3/
H A D	mux.h	`23 * M0 - Mode 0 41 #define M0 0 macro`
/u-boot/arch/arm/include/asm/arch-omap5/
H A D	mux_dra7xx.h	`29 #define M0 0 macro`

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asus-wl-520gu-7.0.1.45
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netbsd-current
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netgear-R7800-V1.0.2.28
netgear-WNDR4500-V1.0.1.40_1.0.68
netgear-WNDR4500v2-V1.0.0.60_1.0.38
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