Searched refs:L1CSR2_DCWS (Results 1 - 3 of 3) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S233 oris r3,r3,(L1CSR2_DCWS)@h
245 andis. r3,r3,(L1CSR2_DCWS)@h
H A Dcpu_init.c707 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
723 if (mfspr(L1CSR2) & L1CSR2_DCWS)
/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h494 #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ macro

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