/u-boot/drivers/pinctrl/renesas/ |
H A D | pfc-r8a77970.c | 121 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 220 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 286 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 640 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 641 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 642 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4), 643 PINMUX_IPSR_GPSR(IP6_31_28, D14), 2294 IP6_31_28
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H A D | pfc-r8a77990.c | 78 #define GPSR0_10 F_(D10, IP6_31_28) 274 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 405 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 913 PINMUX_IPSR_GPSR(IP6_31_28, D10), 914 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), 915 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), 916 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), 917 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), 918 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_ [all...] |
H A D | pfc-r8a77980.c | 136 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28) 254 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 336 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 713 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), 714 PINMUX_IPSR_GPSR(IP6_31_28, SCL4), 715 PINMUX_IPSR_GPSR(IP6_31_28, D14), 716 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6), 2748 IP6_31_28
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H A D | pfc-r8a77995.c | 105 #define GPSR2_18 F_(VI4_DATA17, IP6_31_28) 268 #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 377 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 742 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), 743 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), 2735 IP6_31_28
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H A D | pfc-r8a77965.c | 91 #define GPSR0_12 F_(D12, IP6_31_28) 318 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 468 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 1006 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1007 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1008 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1009 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1010 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1011 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR [all...] |
H A D | pfc-r8a77951.c | 85 #define GPSR0_12 F_(D12, IP6_31_28) 312 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 462 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 999 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1000 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1001 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1002 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1003 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1004 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR [all...] |
H A D | pfc-r8a7796.c | 91 #define GPSR0_12 F_(D12, IP6_31_28) 318 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 468 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ 1004 PINMUX_IPSR_GPSR(IP6_31_28, D12), 1005 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), 1006 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), 1007 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), 1008 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), 1009 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR [all...] |