/u-boot/drivers/pinctrl/renesas/ |
H A D | pfc-r8a77970.c | 122 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 219 #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 285 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 635 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 636 PINMUX_IPSR_GPSR(IP6_27_24, D13), 637 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7), 638 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1), 2295 IP6_27_24
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H A D | pfc-r8a77990.c | 79 #define GPSR0_9 F_(D9, IP6_27_24) 273 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 404 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 905 PINMUX_IPSR_GPSR(IP6_27_24, D9), 906 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), 907 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), 908 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), 909 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), 910 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_ [all...] |
H A D | pfc-r8a77980.c | 137 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24) 253 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 335 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 708 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), 709 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0), 710 PINMUX_IPSR_GPSR(IP6_27_24, D13), 711 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5), 2749 IP6_27_24
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H A D | pfc-r8a77995.c | 106 #define GPSR2_17 F_(VI4_DATA16, IP6_27_24) 267 #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 376 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 739 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), 740 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), 2736 IP6_27_24
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H A D | pfc-r8a77965.c | 92 #define GPSR0_11 F_(D11, IP6_27_24) 317 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 467 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 998 PINMUX_IPSR_GPSR(IP6_27_24, D11), 999 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 1000 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 1001 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1002 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1003 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_ [all...] |
H A D | pfc-r8a77951.c | 86 #define GPSR0_11 F_(D11, IP6_27_24) 311 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 991 PINMUX_IPSR_GPSR(IP6_27_24, D11), 992 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 993 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 994 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 995 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 996 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_ [all...] |
H A D | pfc-r8a7796.c | 92 #define GPSR0_11 F_(D11, IP6_27_24) 317 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 467 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 996 PINMUX_IPSR_GPSR(IP6_27_24, D11), 997 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), 998 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), 999 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), 1000 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), 1001 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_ [all...] |