Searched refs:IP5_27_24 (Results 1 - 7 of 7) sorted by relevance

/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c130 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
211 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
285 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
593 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
594 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
595 PINMUX_IPSR_GPSR(IP5_27_24, D5),
596 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
2285 IP5_27_24
H A Dpfc-r8a77990.c87 #define GPSR0_1 F_(D1, IP5_27_24)
265 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
404 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
841 PINMUX_IPSR_GPSR(IP5_27_24, D1),
842 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
843 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
844 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
845 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
846 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB
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H A Dpfc-r8a77980.c145 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
245 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
335 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
671 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
672 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
673 PINMUX_IPSR_GPSR(IP5_27_24, D5),
674 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
2739 IP5_27_24
H A Dpfc-r8a77995.c114 #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
259 #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
376 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
712 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
2726 IP5_27_24
H A Dpfc-r8a77965.c100 #define GPSR0_3 F_(D3, IP5_27_24)
309 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
467 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
951 PINMUX_IPSR_GPSR(IP5_27_24, D3),
952 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
953 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
954 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5597 IP5_27_24
H A Dpfc-r8a77951.c94 #define GPSR0_3 F_(D3, IP5_27_24)
303 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
944 PINMUX_IPSR_GPSR(IP5_27_24, D3),
945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5400 IP5_27_24
H A Dpfc-r8a7796.c100 #define GPSR0_3 F_(D3, IP5_27_24)
309 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
467 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
949 PINMUX_IPSR_GPSR(IP5_27_24, D3),
950 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
5356 IP5_27_24

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