Searched refs:IP4_27_24 (Results 1 - 7 of 7) sorted by relevance

/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c102 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
203 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
285 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
556 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
557 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
558 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
559 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
2275 IP4_27_24
H A Dpfc-r8a77990.c98 #define GPSR1_15 F_(A15, IP4_27_24)
257 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
404 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
783 PINMUX_IPSR_GPSR(IP4_27_24, A15),
784 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
785 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
786 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
787 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
788 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB
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H A Dpfc-r8a77980.c117 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
237 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
335 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
635 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
636 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
637 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
2729 IP4_27_24
H A Dpfc-r8a77995.c58 #define GPSR1_31 F_(QPOLB, IP4_27_24)
251 #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
376 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
687 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
688 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
2716 IP4_27_24
H A Dpfc-r8a77965.c111 #define GPSR1_23 F_(RD_N, IP4_27_24)
301 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
467 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
897 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
898 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
899 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
901 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
902 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_
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H A Dpfc-r8a77951.c105 #define GPSR1_23 F_(RD_N, IP4_27_24)
295 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
461 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
890 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
891 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
892 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
894 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
895 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_
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H A Dpfc-r8a7796.c111 #define GPSR1_23 F_(RD_N, IP4_27_24)
301 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
467 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
895 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
896 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
897 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_
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