/u-boot/drivers/pinctrl/renesas/ |
H A D | pfc-r8a77970.c | 98 #define GPSR1_0 F_(IRQ0, IP2_27_24) 187 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 276 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 483 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 2255 IP2_27_24
|
H A D | pfc-r8a77990.c | 116 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24) 239 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 395 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 650 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), 651 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), 652 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE), 653 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), 654 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), 655 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_ [all...] |
H A D | pfc-r8a77995.c | 74 #define GPSR1_15 F_(DU_DG7, IP2_27_24) 233 #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 367 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 622 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), 623 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), 624 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), 2696 IP2_27_24
|
H A D | pfc-r8a77965.c | 127 #define GPSR1_7 F_(A7, IP2_27_24) 283 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 458 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 795 PINMUX_IPSR_GPSR(IP2_27_24, A7), 796 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 797 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 798 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 799 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 800 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA1 [all...] |
H A D | pfc-r8a77951.c | 121 #define GPSR1_7 F_(A7, IP2_27_24) 279 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 452 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 788 PINMUX_IPSR_GPSR(IP2_27_24, A7), 789 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 790 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 791 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 792 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 793 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA1 [all...] |
H A D | pfc-r8a7796.c | 127 #define GPSR1_7 F_(A7, IP2_27_24) 283 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 458 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 793 PINMUX_IPSR_GPSR(IP2_27_24, A7), 794 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), 795 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), 796 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), 797 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), 798 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA1 [all...] |
H A D | pfc-r8a77980.c | 100 #define GPSR1_0 F_(IRQ0, IP2_27_24) 221 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro 326 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ 567 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), 2709 IP2_27_24
|