Searched refs:IP0_27_24 (Results 1 - 7 of 7) sorted by relevance

/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c62 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
171 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
276 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
418 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
419 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
420 PINMUX_IPSR_GPSR(IP0_27_24, A6),
2235 IP0_27_24
H A Dpfc-r8a77995.c47 #define GPSR0_8 F_(MLB_SIG, IP0_27_24)
217 #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
367 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
556 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
557 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
558 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
559 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
2676 IP0_27_24
H A Dpfc-r8a77980.c64 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
205 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
326 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
491 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
492 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
493 PINMUX_IPSR_GPSR(IP0_27_24, A6),
2689 IP0_27_24
H A Dpfc-r8a77990.c134 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
223 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
395 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
578 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
579 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
580 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
581 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
4793 IP0_27_24
H A Dpfc-r8a77965.c151 #define GPSR2_0 F_(IRQ0, IP0_27_24)
267 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
458 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
681 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
682 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
683 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
684 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_
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H A Dpfc-r8a77951.c145 #define GPSR2_0 F_(IRQ0, IP0_27_24)
261 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
452 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
674 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
675 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
676 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
677 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
679 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_
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H A Dpfc-r8a7796.c151 #define GPSR2_0 F_(IRQ0, IP0_27_24)
267 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
458 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_
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