Searched refs:IDC_ENABLE (Results 1 - 4 of 4) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c22 mtspr(IC_CST, IDC_ENABLE);
40 mtspr(DC_CST, IDC_ENABLE);
H A Dcpu.c72 wr_ic_cst(IDC_ENABLE);
110 wr_dc_cst(IDC_ENABLE);
H A Dstart.S104 lis r3, IDC_ENABLE@h /* Enable instruction cache */
/u-boot/arch/powerpc/include/asm/
H A Dcache.h79 #define IDC_ENABLE 0x02000000 /* Cache enable */ macro

Completed in 46 milliseconds